3D7608 & 3D7612
APPLICATION NOTES
error is less than 1.0 LSB at every address (see
GENERAL INFORMATION
Table 1).
Figure 1 illustrates the main functional blocks of
the 3D7608 & 3D7612. Since these devices are
CMOS designs, all unused input pins must be
returned to well-defined logic levels, VDD or
Ground.
The absolute error is defined as follows:
eabs = tPW – (tinh + addr * tinc)
where tinh is the nominal inherent delay. The
absolute error is limited to 1.5 LSB or 3.0 ns,
whichever is greater, at every address.
The pulse generator architecture is comprised of
a number of delay cells (for fine control) and an
oscillator & counter (for coarse control). Each
device is individually trimmed for maximum
accuracy and linearity throughout the address
range. The change in pulse width from one
address setting to the next is called the
The inherent pulse width error is the deviation of
the inherent width from its nominal value. It is
limited to 2.0 ns from the nominal inherent pulse
width of 10 ns.
increment, or LSB. It is nominally equal to the
device dash number. The minimum pulse width,
achieved by setting the address to zero, is called
the inherent pulse width.
PULSE WIDTH STABILITY
The characteristics of CMOS integrated circuits
are strongly dependent on power supply and
temperature. The 3D7608 & 3D7612 utilize novel
compensation circuitry to minimize the
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
performance variations induced by fluctuations in
power supply and/or temperature.
With regard to stability, the output pulse width of
the 3D7608 & 3D7612 at a given address, addr,
can be split into two components: the inherent
pulse width (tinh) and the relative pulse width (tPW
- tinh). These components exhibit very different
stability coefficients, both of which must be
considered in very critical applications.
PULSE WIDTH ACCURACY
There are a number of ways of characterizing the
pulse width accuracy of a programmable pulse
generator. The first is the differential nonlinearity
(DNL), also referred to as the increment error. It
is defined as the deviation of the increment at a
given address from its nominal value. For most
dash numbers, the DNL is within 0.5 LSB at
every address (see Table 1: Pulse Width Step).
The thermal coefficient of the relative pulse width
is limited to ±250 PPM/C, which is equivalent to a
variation, over the -40C to 85C operating range,
of ±1.5% from the room-temperature pulse width.
This holds for all dash numbers. The thermal
coefficient of the inherent pulse width is
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the pulse-width-versus-
address data. The INL is then the deviation of a
given width from this line. For all dash numbers,
the INL is within 1.0 LSB at every address.
nominally +10ps/C for dash numbers less than 1,
and +15ps/C for all other dash numbers.
The power supply sensitivity of the relative pulse
width is ±0.5% over the 4.75V to 5.25V operating
range, with respect to the pulse width at the
nominal 5.0V power supply. This holds for all
dash numbers. The sensitivity of the inherent
pulse width is nominally –1ps/mV for all dash
numbers.
The relative error is defined as follows:
erel = (tPW – tinh) – addr * tinc
where addr is the address, tPW is the measured
width at this address, tinh is the measured
inherent width, and tinc is the nominal increment.
It is very similar to the INL, but simpler to
calculate. For most dash numbers, the relative
It should also be noted that the DNL is also
adversely affected by thermal and supply
variations, particularly at the MSL/LSB
crossovers (ie, 63 to 64, 127 to 128, etc).
Doc #06009
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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