Datasheet > 逻辑 > 延迟线> 3D7608R-5K

3D7608R-5K

更新时间： 2024-02-25 04:20:09

品牌	Logo	应用领域
DATADELAY		延迟线逻辑集成电路脉冲光电二极管脉冲发生器
页数	文件大小	规格书
7页	352K
描述
8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

3D7608R-5K 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
系列：	7608	JESD-30 代码：	R-PDSO-G16
长度：	10.335 mm	逻辑集成电路类型：	PULSE GENERATOR DELAY LINE
功能数量：	1	抽头/阶步数：	255
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	可编程延迟线：	YES
认证状态：	Not Qualified	座面最大高度：	2.71 mm
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.51 mm	Base Number Matches：	1

3D7608R-5K 数据手册

3D7608 & 3D7612

APPLICATION NOTES (CONT’D)

TRIGGER & RESET TIMING

ADDRESS UPDATE

Figure 2 shows the timing diagram of the device

when the reset input (RES) is not used. In this

case, the pulse is triggered by the rising edge of

the TRIG signal and ends at a time determined

by the address loaded into the device. While the

pulse is active, any additional triggers occurring

are ignored. Once the pulse has ended, and after

a short recovery time, the next trigger is

The 3D7608/3D7612 can operate in one of two

addressing modes. In the transparent mode (AE

held high), the parallel address inputs must

persist for the duration of the output pulse, in

accordance with Figure 4. In the latched mode,

the address data is stored internally, which

allows the parallel inputs to be connected to a

multi-purpose data bus. Timing for this mode is

also shown in Figure 4.

recognized. Figure 3 shows the timing for the

case where a reset is issued before the pulse

has ended. Again, there is a short recovery time

required before the next trigger can occur.

TRIGGER

RESET

TRG

RES

OUT

INPUT

LOGIC

DELAY

LINE

OSCILLATOR/

COUNTER

OUTPUT

LOGIC

OUTB

PULSE OUT

BIT-SHIFT LOGIC

ADDR ENABLE

8- OR 12-BIT LATCH

P10 P11

P0 P1

P7 P8 P9

Figure 1: Functional block diagram

t_TW

TRIG

t_ID

t_PW

t_RTO

OUT

OUTB

Figure 2: Timing Diagram (RES=0)

t_TW

TRIG

RES

t_RTR

t_RW

t_ID

t_RD

OUT

OUTB

Figure 3: Timing Diagram (with reset)

Doc #06009

5/8/2006

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

1 234 5 6 7

下载PDF

与3D7608R-5K相关器件

型号	品牌	描述	获取价格	数据表
3D7608R-800K	DATADELAY	8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS	获取价格
3D7608W-200K	DATADELAY	Pulse Generator Delay Line, Programmable, 1-Func, 255-Tap, True Output, CMOS, PDSO20, ROHS	获取价格
3D7608W-500K	DATADELAY	Pulse Generator Delay Line, Programmable, 1-Func, 255-Tap, True Output, CMOS, PDSO20, ROHS	获取价格
3D7608W-800K	DATADELAY	Pulse Generator Delay Line, Programmable, 1-Func, 255-Tap, True Output, CMOS, PDSO20, ROHS	获取价格
3D7612	DATADELAY	8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS	获取价格
3D7612W-0.25	DATADELAY	8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS	获取价格