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3D7522H-50 PDF预览

3D7522H-50

更新时间: 2024-01-15 08:31:32
品牌 Logo 应用领域
DATADELAY 电信光电二极管电信集成电路
页数 文件大小 规格书
4页 274K
描述
Manchester Decoder, CMOS, PDSO8, 0.300 INCH, ROHS COMPLIANT, GULLWING, DIP-8

3D7522H-50 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.72Is Samacsys:N
JESD-30 代码:R-PDSO-G8长度:9.46 mm
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:4.57 mm标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:MANCHESTER DECODER温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

3D7522H-50 数据手册

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3D7522  
DEVICE SPECIFICATIONS  
TABLE 2: ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
DC Supply Voltage  
Input Pin Voltage  
Input Pin Current  
Storage Temperature  
Lead Temperature  
SYMBOL  
VDD  
MIN  
-0.3  
-0.3  
-10  
MAX  
7.0  
UNITS NOTES  
V
V
VIN  
VDD+0.3  
10  
IIN  
TSTRG  
TLEAD  
mA  
C
25C  
-55  
150  
300  
C
10 sec  
TABLE 3: DC ELECTRICAL CHARACTERISTICS  
(-40C to 85C, 4.75V to 5.25V)  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
mA  
V
NOTES  
Static Supply Current*  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
High Level Output Current  
IDD  
VIH  
VIL  
IIH  
5
2.0  
0.8  
1.0  
1.0  
-4.0  
V
VIH = VDD  
VIL = 0V  
VDD = 4.75V  
VOH = 2.4V  
VDD = 4.75V  
VOL = 0.4V  
CLD = 5 pf  
µA  
IIL  
IOH  
µA  
mA  
Low Level Output Current  
IOL  
4.0  
mA  
ns  
Output Rise & Fall Time  
TR & TF  
2
*IDD(Dynamic) = 2 * CLD * VDD * F  
Input Capacitance = 10 pf typical  
Output Load Capacitance (CLD) = 25 pf max  
where: CLD = Average capacitance load/pin (pf)  
F = Input frequency (GHz)  
TABLE 4: AC ELECTRICAL CHARACTERISTICS  
(-40C to 85C, 4.75V to 5.25V, except as noted)  
SYMBOL  
PARAMETER  
MIN  
5
TYP  
MAX  
50  
UNITS  
MBaud  
MBaud  
NOTES  
Nominal Input Baud Rate  
Allowed Input Baud Rate Deviation  
fBN  
fB  
-0.15 fBN  
0.15 fBN  
0C to 70C  
25C, 5.00V  
Allowed Input Baud Rate Deviation  
Allowed Input Baud Rate Deviation  
fB  
fB  
-0.05 fBN  
-0.03 fBN  
0.05 fBN  
0.03 fBN  
MBaud 4.75V to 5.25V  
MBaud  
-55C to 125C  
4.75V to 5.25V  
Allowed Input Duty Cycle  
Bit Cell Time  
42.5  
50.0  
1000/fB  
0.75 tc  
500/fBN  
4.0  
57.5  
%
ns  
ns  
ns  
ns  
tc  
tCL  
Input Data Edge to Clock Falling Edge  
Clock Width Low  
tCWL  
±2ns or 5%  
Clock Falling Edge to Data Transition  
tCD  
3.0  
5.0  
Doc #06002  
5/8/2006  
DATA DELAY DEVICES, INC.  
3
3 Mt. Prospect Ave. Clifton, NJ 07013  

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