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357VD3C80M0000 PDF预览

357VD3C80M0000

更新时间: 2024-01-08 06:21:50
品牌 Logo 应用领域
西迪斯 - CTS /
页数 文件大小 规格书
4页 134K
描述
Oscillator

357VD3C80M0000 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.57
JESD-609代码:e4端子面层:Gold (Au) - with Nickel (Ni) barrier
Base Number Matches:1

357VD3C80M0000 数据手册

 浏览型号357VD3C80M0000的Datasheet PDF文件第1页浏览型号357VD3C80M0000的Datasheet PDF文件第3页浏览型号357VD3C80M0000的Datasheet PDF文件第4页 
Model 357  
7x5mm Low Cost  
CMOS/TTL Compatible VCXO  
ELECTRICAL CHARACTERISTICS  
PARAMETER  
Maximum Supply Voltage  
Maximum Control Voltage  
Storage Temperature  
Frequency Range  
SYMBOL  
VCC  
VC  
TSTG  
fO  
CONDITIONS  
MIN  
-0.5  
-0.5  
-55  
TYP  
MAX  
7.0  
VCC  
125  
80  
UNIT  
V
V
°C  
MHz  
-
-
-
-
-
-
-
-
1.5  
20, 25 or  
Frequency Stability  
(See Note 1 and Ordering Information)  
f/fO  
-
-
-
-
-
± ppm  
± ppm  
50  
50, 80 or  
100  
Absolute Pull Range  
(See Note 2 and Ordering Information)  
APR  
-
Operating Temperature  
Commercial  
Industrial  
Supply Voltage  
Model 357S, 357W  
Model 357L, 357V  
Supply Current  
TA  
-
°C  
V
-20  
-40  
70  
85  
25  
± 10 %  
VCC  
4.5  
2.97  
5.0  
3.3  
5.5  
3.63  
CL = 15 pF  
1.5 MHz to 20 MHz  
20.1 MHz to 40 MHz  
40.1 MHz to 60 MHz  
60.1 MHz to 80 MHz  
-
-
-
-
-
5
8
10  
12  
-
20  
30  
40  
45  
30  
ICC  
mA  
CL  
VC  
Output Load  
pF  
V
Control Voltage  
Model 357S, 357W  
Model 357L, 357V  
Frequency Deviation  
Linearity  
V
V
CC = 5.0V  
CC = 3.3V  
0.5  
0.3  
-
2.5  
3.3  
135  
5
8
-
4.5  
3.0  
-
10  
15  
55  
f  
L
25°C at Time of Shipment, over VC range  
< 52 MHz  
> 52 MHz  
@ 50% Level  
± ppm  
%
-
Best Straight Line Fit  
Output Duty Cycle  
Output Voltage Levels  
Logic '1' Level  
SYM  
45  
%
VOH  
VOL  
90%VCC  
-
V
CMOS Load  
CMOS Load  
-
-
-
10%VCC  
Logic '0' Level  
Output Current Levels  
Logic '1' Level  
Logic '0' Level  
Rise and Fall Time  
Input Impedance  
Transfer Function  
Start Up Time  
Modulation Roll-off  
Phase Jitter  
mA  
IOH  
IOL  
TR, TF  
ZC  
-
TS  
CMOS Load  
CMOS Load  
@ 10% - 90% Levels  
-
-
-
50  
-
-
-
-
3.5  
-
-14  
14  
5.0  
-
-
10  
-
ns  
kOhms  
-
ms  
kHz  
-
-
Positive  
Application of VCC  
@ -3dB  
Bandwidth 12 kHz - 20 MHz  
-
-
-
-
10  
-
tjms  
1
ps RMS  
Enable Function  
Enable Input Voltage  
Disable Input Voltage  
Enable Time  
Notes:  
VIH  
VIL  
TPLZ  
Pin 2 or Pin 5 Logic '1', Output Enabled  
Pin 2 or Pin 5 Logic '0', Output Disabled  
Pin 2 or Pin 5 Logic '1'  
2.5  
-
-
-
-
-
-
V
0.5  
100  
ns  
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 20 year aging at an average operating temperature  
of +40 °C.  
2. Minimum guaranteed frequency shift from fO over variations in temperature, aging, power supply and load at an average operating temperature  
of +40°C for 10 years.  
SINGLE SIDE BAND PHASE NOISE  
(typical maximum)  
Frequency  
Offset  
Phase Noise  
(dBc/Hz) *  
Frequency  
Offset  
Phase Noise  
(dBc/Hz) *  
10 Hz  
100 Hz  
1k Hz  
-60  
-90  
-112  
10k Hz  
100k Hz  
100k Hz  
-130  
-150  
-150  
* Results may vary depending on frequency.  
Document No. 008-0244-0  
Page 2 - 4  
Rev. G  
٠
 
٠
 
٠
 CTS Communications Components, Inc.
٠
 171 Covington Drive
٠
 Bloomingdale, IL 60108
٠
 630-924-3500
٠
 
٠
 
٠  

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