Datasheet > 33905

33905

更新时间： 2022-09-18 16:10:51

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
91页	1665K
描述
System Basis Chip Gen2 with High Speed CAN and LIN Interface

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数据手册

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33905 数据手册

INTERNAL BLOCK DIAGRAM

VBAUX VCAUX

VSUP1

VAUX

5 V Auxiliary

Regulator

VSUP2

SAFE

VDD

V_DDRegulator

S2-INT

RST

INT

Fail-safe

Power Management

State Machine

DBG

GND

MOSI

SCLK

Oscillator

SPI

MISO

VSENSE

Analog Monitoring

Signals Condition & Analog MUX

MUX-OUT

5V-CAN

S2-INT

I/O-0

I/O-1

I/O-3

5 V-CAN

Regulator

Configurable

Input-Output

CANH

SPLIT

CANL

Enhanced High-speed CAN

Physical Interface

TXD

RXD

S2-INT

TXD-L

RXD-L

LIN Term #1

LIN-T

LIN

LIN 2.1 Interface - #1

Figure 5. 33905S Internal Block Diagram

33904/5

Analog Integrated Circuit Device Data

Freescale Semiconductor

1...3 4 567 8 9...91

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