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33902

更新时间： 2022-12-14 19:14:06

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
31页	700K
描述
High Speed CAN Interface with Embedded 5.0 V Supply

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33902 数据手册

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 27 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

LOGIC INPUT PINS (EN, STBY, TXD)

High Level Input Voltage

Symbol

Min

Typ

Max

Unit

V_IH

V_IL

0.7 VIO

Low Level Input Voltage

0.3 VIO

Pull-down Current, EN, STBY, V_IN= V_IO

Pull-up Current, TXD, V_IN= 0 V

I_{PD EN-STBY}

I_{PD TXD}

1.0

4.0

µA

-250

DATA OUTPUT PINS (RXD) AND (ERR)

Low Level Output Voltage

I = 5.0 mA

VOUT_LOW

VOUT_HIGH

IOUT_HIGH

IOUT_LOW

0.0

0.7 VIO

-12

0.3 VIO

VIO

High Level Output Voltage

I = -3.0 mA

High Level Output Current

V = VIO - 0.4 V

-5.0

5.0

-2.0

Low Level Output Current

V = 0.4 V

2.0

OUTPUT PIN (INH)

Output Drop Voltage (I_INH), I_OUT= 100 uA)

leakage Current (Sleep mode)

INPUT PIN (WAKE)

INH_DROP

INH_LEAK

0.05

0.2

0.8

5.0

µA

Low level threshold voltage

High level threshold voltage

WAKE_LTH

WAKE_HTH

IWAKE_IN

2.0

-10

2.5

2.7

3.0

3.5

Input Current

µA

V_WAKE= -0.2 to 18 V

LOGIC INPUT/OUTPUT PINS (CANH, CANL)

Bus pins common mode voltage for full functionality

Differential input voltage, recessive state at RXD

Differential input voltage, dominant state at RXD

Differential input hysteresis (RXD)

V_COM

-12

V_CANH-VCANL-R

500

kΩ

V_CANH-VCANL-D

V_DIFF-HYST

900

100

Input resistance

R_IN

R_IND

5.0

-3.0

Differential input resistance

100

3.0

Common mode input resistance matching

R_INM

V_CANH

0.0

CANH output voltage(45 Ω < R_BUS< 65 Ω)

TX dominant state

2.75

2.0

3.5

2.5

4.5

3.0

TX recessive state

CANL output voltage(45 Ω < R_BUS< 65 Ω)

TX dominant state

V_CANL

0.5

2.0

1.5

2.5

2.25

3.0

TX recessive state

Differential output voltage(45 Ω < R_BUS< 65 Ω)

TX dominant state

V_OH-V_OL

1.5

2.0

0.0

3.0

TX recessive state

-500

33902

Analog Integrated Circuit Device Data

Freescale Semiconductor

1...3 4 567 8 9...31

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