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33887_08 PDF预览

33887_08

更新时间: 2022-12-18 11:41:31
品牌 Logo 应用领域
飞思卡尔 - FREESCALE /
页数 文件大小 规格书
37页 1638K
描述
5.0 A H-Bridge with Load Current Feedback

33887_08 数据手册

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PIN CONNECTIONS  
Transparent Top View of Package  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
1
2
NC  
D2  
NC  
D1  
IN2  
EN  
V+  
V+  
3
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
FB  
4
5
6
7
NC  
AGND  
FS  
8
9
10  
NC  
NC  
Figure 4. 33887 Pin Connections  
Table 2. PQFN PIN DEFINITIONS  
A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.  
Pin  
Pin Name  
Formal Name  
Definition  
No internal connection to this pin.  
1, 7, 10, 16,  
19, 28, 31  
NC  
No Connect  
Active HIGH input used to simultaneously tri-state disable both H-Bridge  
outputs. When D1 is Logic HIGH, both outputs are tri-stated.  
2
D1  
Disable 1  
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).  
3
4
IN2  
EN  
Logic Input Control 2  
Enable  
Logic input Enable control of device (i.e., EN logic HIGH = full operation,  
EN logic LOW = Sleep Mode).  
Positive supply connections.  
5, 6, 12, 13, 34, 35  
V+  
AGND  
FS  
Positive Power Supply  
Analog Ground  
Low-current analog signal ground.  
8
9
Open drain active LOW Fault Status output requiring a pull-up resistor to  
5.0 V.  
Fault Status for H-Bridge  
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).  
Output 1 of H-Bridge.  
11  
14, 15, 17, 18  
20  
IN1  
OUT1  
FB  
Logic Input Control 1  
H-Bridge Output 1  
Current feedback output providing ground referenced 1/375th ratio of  
H-Bridge high-side current.  
Feedback for H-Bridge  
High-current power ground.  
21–26  
27  
PGND  
D2  
Power Ground  
Disable 2  
Active LOW input used to simultaneously tri-state disable both H-Bridge  
outputs. When D2 is Logic LOW, both outputs are tri-stated.  
Output 2 of H-Bridge.  
29, 30, 32, 33  
36  
OUT2  
CCP  
H-Bridge Output 2  
External reservoir capacitor connection for internal charge pump  
capacitor.  
Charge Pump Capacitor  
Exposed pad thermal interface for sinking heat from the device.  
Note: Must be DC-coupled to analog ground and power ground via very  
low impedance path to prevent injection of spurious signals into IC  
substrate.  
Pad  
Thermal  
Interface  
Exposed Pad Thermal  
Interface  
33887  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4

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