Datasheet > 33886

33886

更新时间： 2022-02-14 13:42:35

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
21页	554K
描述
The 33886 is a monolithic H-Bridge ideal for fractional horsepower DC-motor and bi-directional thrust solenoid control. The IC incorporates internal control logic, charge pump, gate drive, and low RDS(ON) MOSFET output circuitry. The 33886 is able to control continuous inductive DC load currents up to 5.0 A. Output loads can be pulse width modulated (PWM-ed) at frequencies up to 10 kHz

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33886 数据手册

Freescale Semiconductor, Inc.

DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ T_A≤ 125°C unless otherwise noted. Typical values noted

reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TIMING CHARACTERISTICS

PWM Frequency (Note 20)

–

kHz

µs

f_PWM

f_MAX

Maximum Switching Frequency During Active Current Limiting (Note 21)

Output ON Delay (Note 22)

V+ = 14 V

d(ON)

–

Output OFF Delay (Note 22)

V+ = 14 V

µs

t_d(OFF)

t_f, t_r

Output Rise and Fall Time (Note 23)

V+ = 14 V, I

= 3.0 A

2.0

100

–

5.0

20.5

16.5

–

8.0

–

OUT

Output Latch-OFF Time

µs

t_a

t_b

Output Blanking Time

Output FET Body Diode Reverse Recovery Time (Note 24)

Disable Delay Time (Note 25)

–

8.0

–

t_d(disable)

t_FAULT

t_pod

Short Circuit/Overtemperature Turn-OFF Time (Note 26)

Power-OFF Delay Time

–

4.0

1.0

–

5.0

Notes

20. The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM pulse

train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. Refer

to Typical Switching Waveforms, Figures 11 through 18, pp. 12–13.

21. The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant OFF-

time PWM of the output. The output load current effects the Maximum Switching Frequency.

22. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition

direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the 90%

point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to the 10%

point of the output response signal. See Figure 2, page 8.

23. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4, page 8.

24. Parameter is guaranteed by design but not production tested.

25. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 3,

page 8.

26. Increasing currents will become limited at I . Hard shorts will breach the I

or I

limit, forcing the output into an immediate tri-state

SCL

LIM

SCH

latch-OFF. See Figures 6 and 7, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature above 160°C

will cause the active current limiting to progressively "fold back" (or decrease) to 2.5 A typical at 175°C where thermal latch-OFF will occur.

See Figure 5, page 8.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33886

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