CY7C1339
128K x 32 Synchronous-Pipelined Cache RAM
The CY7C1339 I/O pins can operate at either the 2.5V or the
Features
3.3V level; the I/O pins are 3.3V tolerant when V
=2.5V.
DDQ
• Supports 100-MHz bus for Pentium and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined oper-
ation
• 128K by 32 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1339 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
• User-selectable burst counter supporting Intel Pen-
tium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
Byte write operations are qualified with the four Byte Write
Select (BW
) inputs. A Global Write Enable (GW) overrides
• JEDEC-standard 100 TQFP pinout
[3:0]
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
Three synchronous Chip Selects (CE , CE , CE ) and an
1
2
3
The CY7C1339 is a 3.3V, 128K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
MODE
Logic Block Diagram
2
(A
)
[1;0]
Q
0
CLK
ADV
ADSC
BURST
COUNTER
CE
CLR
Q
1
ADSP
Q
15
17
ADDRESS
REGISTER
CE
D
128KX32
MEMORY
ARRAY
A
[16:0]
17
15
GW
Q
Q
Q
Q
DQ[31:24]
D
BYTEWRITE
REGISTERS
BWE
BW
3
D
D
D
DQ[23:16]
BYTEWRITE
REGISTERS
BW
2
DQ[15:8]
BYTEWRITE
REGISTERS
BW
1
DQ[7:0]
BYTEWRITE
REGISTERS
BW
0
32
32
CE
1
2
CE
D
CE
ENABLE
REGISTER
CLK
Q
CE
3
D
Q
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
Intel and Pentium are trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 8, 2000
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