Datasheet > 存储 > EEPROM> 24LC64T-E/MC16KVAO

24LC64T-E/MC16KVAO

更新时间： 2024-01-08 16:47:13

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数	文件大小	规格书
44页	1309K
描述
EEPROM, 8KX8, Serial, CMOS, PDSO8

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24LC64T-E/MC16KVAO 技术参数

生命周期：	Active	包装说明：	TSSOP,
Reach Compliance Code：	compliant	风险等级：	5.64
最大时钟频率 (fCLK)：	0.4 MHz	JESD-30 代码：	R-PDSO-G8
长度：	4.4 mm	内存密度：	65536 bit
内存集成电路类型：	EEPROM	内存宽度：	8
功能数量：	1	端子数量：	8
字数：	8192 words	字数代码：	8000
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	8KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：	SERIAL	筛选级别：	TS 16949
座面最大高度：	1.2 mm	串行总线类型：	I2C
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	3 mm
最长写入周期时间 (tWC)：	5 ms	Base Number Matches：	1

24LC64T-E/MC16KVAO 数据手册

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24AA64/24LC64/24FC64

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Rotated

Name PDIP SOIC TSSOP

DFN⁽¹⁾TDFN⁽¹⁾MSOP SOT-23 CS

Description

TSSOP

—

Chip Address Input

Ground

VSS

SDA

SCL

VCC

Serial Address/Data I/O

Serial Clock

Write-Protect Input

+1.7V to 5.5V Power Supply

Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.

2.1

A0, A1, A2 Chip Address Inputs

2.3

Serial Clock (SCL)

The A0, A1 and A2 inputs are used by the 24XX64 for

multiple device operation. The levels on these inputs

are compared with the corresponding bits in the slave

address. The chip is selected if the compare is true.

The SCL input is used to synchronize the data transfer

from and to the device.

2.4

Write-Protect (WP)

Up to eight devices may be connected to the same bus

by using different Chip Select bit combinations. These

inputs must be connected to either VCC or VSS.

This pin must be connected to either VSS or VCC. If tied

to VSS, write operations are enabled. If tied to VCC,

write operations are inhibited but read operations are

not affected.

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microcontroller or other programmable device, the chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed. Address

pins are not available in the SOT-23 or Chip Scale

packages.

3.0

FUNCTIONAL DESCRIPTION

The 24XX64 supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24XX64 works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

2.2

Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses

and data into and out of the device. Since it is an open-

drain terminal, the SDA bus requires a pull-up resistor

to VCC (typical 10 k for 100 kHz, 2 kfor 400 kHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

 1997-2012 Microchip Technology Inc.

DS21189T-page 5

1 2 3 456 7 8...44

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