Datasheet > 2309M-1LF

2309M-1LF

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
10页	238K
描述
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16

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2309M-1LF 数据手册

ICS2309

3.3 VOLT ZERO DELAY LOW SKEW BUFFER

ZERO DELAY BUFFERS

Pin Assignment

CLKIN

CLKA1

CLKA2

VDD

CLKOUT

CLKA4

CLKA3

VDD

GND

CLKB1

CLKB2

CLKB4

CLKB3

16 pin narrow (150 mil) SOIC

Output Clock Mode Select Table

CLKA1:A4

Tri-state (note 1)

Running

CLKB1:B4

Tri-state (note 1)

Running

A & B Source

PLL

CLKOUT

Driven

PLL Status

OFF

PLL

Driven

Running

CLKIN (note 2)

PLL

PLL Bypass Mode

Driven

OFF

Running

Note 1. Outputs are in high impedance state

Note 2. Buffer mode only; not zero delay between input and output

Pin Descriptions

Pin Type

Pin Description

Number

Name

2 - 3

CLKIN

CLKA1:A4

VDD

Input

Clock input (5 V tolerant).

Output Clock outputs A1:A4. See table above.

Power

Power supply. Connect to 3.3 V.

Connect to ground.

GND

6 - 7

CLKB1:B4

Output Clock outputs B1:B4. See table above.

Input

Select input 2. See table above. Internal pull-up.

Select input 1. See table above. Internal pull-up.

10 - 11

CLKB1:B4

GND

Output Clock outputs B1:B4. See table above.

Power

Connect to ground.

VDD

Power supply. Connect to 3.3 V.

14 - 15

CLKA1:A4

CLKOUT

Output Clock outputs A1:A4. See table above.

Input

Buffered output. Internal feedback on this pin.

IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER

ICS2309

REV F 041906

123 4 5 6 7...10

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