Datasheet > 2308-5HPGI8

2308-5HPGI8

更新时间： 2023-01-02 19:24:06

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
14页	169K
描述
Clock Driver, PDSO16

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数据手册

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2308-5HPGI8 数据手册

IDT2308

3.3VZERODELAYCLOCKMULTIPLIER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

ZERO DELAY AND SKEW CONTROL

To close the feedback loop of the IDT2308, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will

be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust

theinput-outputdelay.

For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay

adjustments are required, use the Output Load Difference Chart to calculate loading differences between the feedback output and remaining outputs.

Ensure the outputs are loaded equally, for zero output-output skew.

REF TO CLKA/CLKB DELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS

1500

1000

500

-30

-25

-20

-15

-10

-5

-500

-1000

-1500

OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS ( pF)

1 2 345 6 7...14

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