Flexible, Robust Design
Additional Features
The 21555 supports either asynchronous or synchronous
primary and secondary clocks. The chip’s I2O-compliant
controller uses local memory for Inbound and Outbound
List storage with on-chip prefetch and posting buffers,
giving lower latency access.
The 21555 Non-Transparent design provides an advanced
transaction forwarding engine, including deeper read and
write buffers, support for more simultaneous transactions,
more flexible ordering mechanisms, and more performance
tuning options.
The 21555 includes a parallel ROM interface that can be
used to attach the Expansion ROM for the subsystem. The
ROM interface can also function as a generic 8-bit
multiplexed interface with programmable read, write and
ready signals to allow attachment on external devices.
The chip also includes a secondary bus arbiter
implementing a 2-level rotating priority algorithm,
supporting nine external bus masters. In addition to
incorporating a JTAG interface, the 21555 implements
compact PCI hot swap support, enabling the 21555 to serve
as a hot swap controller on a compact PCI card.
As a 3.3-volt device with 5.0-volt-tolerant receivers, the
21555 reduces power dissipation and enables the design of
universal PCI cards.
The 21555 offers high-bandwidth 64-bit primary and
64-bit secondary PCI interfaces. This interface supports
application designs requiring the high performance
associated with 64-bit buses.
Power Management
The 21555 Non-Transparent PCI-to-PCI bridge chip
complies with the Advanced Configuration Power Interface
(ACPI) and PCI Bus Power Management Interface
specifications. Through serial pre-load, the 21555’s power
management interface can be tailored to vendor-specific
application needs.
Evaluation Design Kit Improves Time-to-market
Specifications
Characteristic
Power supply
Specification
Intel offers a 21555 Evaluation Design Kit that includes all
of the tools option card suppliers need to bring 21555-based
products to market quickly. The kit contains a PCI evaluation
board featuring a 21555 with two PCI slots on the secondary
bus, schematics, gerber files, configuration software and
complete documentation.
Vdd = 3.3 V
+ VI/O = 5 V or 3.3 V
Operating temperature range
Storage temperature range
Power dissipation
0o C to 70o C
-55o C to 125o C
2.5 W maximum @ Vdd = 3.3 V
PCI clock frequency = 66 MHz
Package
304-pin PBGA
Intel Access
Developer’s Site
http://developer.intel.com/
Bridges Home Page
http://developer.intel.com/design/bridge/
Other Intel Support:
http://developer.intel.com/design/litcentr/
Intel Literature Center
(800) 548-4725 7a.m. to 7 p.m. CST (U.S. and Canada)
International locations please contact your local sales office.
General Information Hotline
(800) 628-8686 or (916) 356-3104 5 a.m. to 5 p.m. PST
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to
any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such
products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel
products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent,
copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
*Third-party marks and names are the property of their respective owners.
For more information, visit the Intel Web site at: developer.intel.com
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