Datasheet > 180M-01T

180M-01T

更新时间： 2024-02-12 00:31:48

品牌	Logo	应用领域
艾迪悌 - IDT		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
9页	154K
描述
Clock Generator, 28MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

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技术参数
数据手册

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180M-01T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOIC-8
针数：	8	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.29	其他特性：	ALSO OPERATES AT 5V SUPPLY
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
长度：	4.9 mm	湿度敏感等级：	1
端子数量：	8	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	28 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
主时钟/晶体标称频率：	28 MHz	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER

180M-01T 数据手册

ICS180-01

LOW EMI CLOCK GENERATOR

SSCG

External Components

The ICS180-01 requires a minimum number of external

components for proper operation.

Decoupling Capacitor

A decoupling capacitor of 0.01µF must be connected

between VDD and GND on pins 6 and 3, as close to

these pins as possible. For optimum device

performance, the decoupling capacitor should be

mounted on the component side of the PCB. Avoid the

use of vias in the decoupling circuit.

Series Termination Resistor

When the PCB trace between the clock output and the

load is over 1 inch, series termination should be used.

To series terminate a 50Ωtrace (a commonly used trace

impedance) place a 33Ωresistor in series with the clock

line, as close to the clock output pin as possible. The

nominal impedance of the clock output is 20Ω.

value of these capacitors is given by the following

equation:

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) The 0.01µF decoupling capacitor should be mounted

on the component side of the board as close to the VDD

pin as possible. No vias should be used between the

decoupling capacitor and VDD pin. The PCB trace to

VDD pin should be kept as short as possible, as should

the PCB trace to the ground via.

2) To minimize EMI, the 33Ωseries termination resistor

(if needed) should be placed close to the clock output.

3) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers. Other signal traces should be routed away

from the ICS180-01. This includes signal traces just

underneath the device, or on layers adjacent to the

ground plane layer used by the device.

IDT™ / ICS™ LOW EMI CLOCK GENERATOR

ICS180-01

REV C 081009

1 234 5 6 7...9

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