Datasheet > 16911A

16911A

更新时间： 2022-12-18 04:45:03

品牌	Logo	应用领域
安捷伦 - AGILENT		/
页数	文件大小	规格书
35页	1054K
描述
Logic Analyzer

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数据手册

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16911A 数据手册

Data Acquisition and Stimulus

Timing/State Modules

Agilent logic analyzer modules

offer the speed, features, and

usability your digital development Sample Position mode allows

team needs to quickly debug,

validate, and optimize your

digital system – at a price that

fits your budget.

captured with the highest

accuracy. Auto Threshold and

Identify problem signals over

hundreds of channels simultaneously

As timing and voltage margins

continue to shrink, confidence

in signal integrity becomes an

increasingly vital requirement

in the design validation process.

Eye scan lets you acquire signal

integrity information on all the

buses in your design, under a

wide variety of operating

you to...

• Obtain accurate and

reliable measurements

Accurately measure precise

timing relationships

• Save time during

measurement setup

Make accurate high-speed timing

measurements with 4 GHz

(250 ps) high-speed timing zoom.

A parallel acquisition architecture

provides high-speed timing

measurements simultaneously

through the same probe

• Gain diagnostic clues

and identify problem

signals quickly

conditions, in a matter of

minutes. Identify problem signals

quickly for further investigation

with an oscilloscope. Results can

be viewed for each individual

signal or as a composite of

• Scan all signals and buses

simultaneously or just a few

with other state or timing

multiple signals or buses.

measurements. Timing zoom

stays active all the time with no

tradeoffs. View data at high

resolution over longer periods of

time with 64 K deep timing zoom.

• View results as a composite

display or as individual signals

• See skew between signals

and buses

Automate measurement setup and

quickly gain diagnostic clues

• Find and fix inappropriate

clock thresholds

Quickly get up and running by

automating your measurement

setup process. In addition, the

logic analyzer’s setup/hold

window (or sampling position)

and threshold voltage settings are

automatically determined so that

data on high-speed buses is

• Measure data valid windows

• Identify signal integrity

problems related to rise

times, fall times, data valid

window widths

Figure 1. Identify problem signals quickly by viewing eye

diagrams across all buses and signals simultaneously.

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