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1430G5LL PDF预览

1430G5LL

更新时间: 2024-01-13 17:15:56
品牌 Logo 应用领域
杰尔 - AGERE 时钟
页数 文件大小 规格书
10页 220K
描述
NetLight 1430G5 Type SONET/SDH Long-Reach Transceivers with Clock Recovery

1430G5LL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred包装说明:,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.42JESD-30 代码:R-PDFO-P
JESD-609代码:e0功能数量:1
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FIBER OPTIC峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified标称供电电压:3.3 V
表面贴装:NO电信集成电路类型:ATM/SONET/SDH TRANSCEIVER
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:PIN/PEG端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

1430G5LL 数据手册

 浏览型号1430G5LL的Datasheet PDF文件第1页浏览型号1430G5LL的Datasheet PDF文件第2页浏览型号1430G5LL的Datasheet PDF文件第4页浏览型号1430G5LL的Datasheet PDF文件第5页浏览型号1430G5LL的Datasheet PDF文件第6页浏览型号1430G5LL的Datasheet PDF文件第7页 
NetLight 1430G5 Type SONET/SDH  
Long-Reach Transceivers with Clock Recovery  
Data Sheet, Rev 1.  
August 2001  
Pin Information (continued)  
Table 1. Transceiver Pin Descriptions (continued)  
Pin  
Logic  
Symbol  
Number  
Name/Description  
Family  
Transmitter  
11  
12  
13  
14  
15  
16  
17  
VCCT  
VEET  
TDIS  
Transmitter Power Supply.  
NA  
NA  
Transmitter Signal Ground.  
Transmitter Disable.  
LVTTL  
LVPECL  
LVPECL  
NA  
TD+  
Transmitter DATA In.  
TD–  
Transmitter DATA In Bar.  
Transmitter Signal Ground.  
VEET  
Bmon–  
Laser Diode Bias Current Monitor—Negative End. The laser bias current  
is accessible as a dc-voltage by measuring the voltage developed across pins  
17 and 18.  
NA  
18  
19  
BMON+  
PMON–  
Laser Diode Bias Current Monitor—Positive End. See pin 17 description.  
NA  
NA  
Laser Diode Optical Power Monitor—Negative End. The back-facet diode  
monitor current is accessible as a dc-voltage by measuring the voltage devel-  
oped across pins 19 and 20.  
20  
PMON+  
Laser Diode Optical Power Monitor—Positive End. See pin 19 description.  
NA  
Printed-Wiring Board Layout Considerations  
Electrostatic Discharge  
A fiber-optic receiver employs a very high gain, wide  
bandwidth transimpedance amplifier. This amplifier  
detects and amplifies signals that are only tens of nA in  
amplitude when the receiver is operating near its sensi-  
tivity limit. Any unwanted signal currents that couple  
into the receiver circuitry cause a decrease in the  
receiver's sensitivity and can also degrade the perfor-  
mance of the receiver's signal detect (SD) circuit. To  
minimize the coupling of unwanted noise into the  
receiver, careful attention must be given to the printed-  
wiring board.  
Caution: This device is susceptible to damage as  
a result of electrostatic discharge (ESD).  
Take proper precautions during both  
handling and testing. Follow EIA® Stan-  
dard EIA-625.  
Although protection circuitry is designed into the  
device, take proper precautions to avoid exposure to  
ESD.  
Agere Systems employs a human-body model (HBM)  
for ESD-susceptibility testing and protection-design  
evaluation. ESD voltage thresholds are dependent on  
the critical parameters used to define the model. A  
standard HBM (resistance = 1.5 k, capacitance =  
100 pF) is widely used and, therefore, can be used for  
comparison purposes. The HBM ESD threshold estab-  
lished for the 1430G5 transceiver is ±1000 V.  
At a minimum, a double-sided printed-wiring board  
(PWB) with a large component-side ground plane  
beneath the transceiver must be used. In applications  
that include many other high-speed devices, a multi-  
layer PWB is highly recommended. This permits the  
placement of power and ground on separate layers,  
which allows them to be isolated from the signal lines.  
Multilayer construction also permits the routing of sen-  
sitive signal traces away from high-level, high-speed  
signal lines. To minimize the possibility of coupling  
noise into the receiver section, high-level, high-speed  
signals such as transmitter inputs and clock lines  
should be routed as far away as possible from the  
receiver pins.  
Application Information  
The 1430 receiver section is a highly sensitive fiber-  
optic receiver. Although the data outputs are digital  
logic levels (LVPECL), the device should be thought of  
as an analog component. When laying out system  
application boards, the 1430 transceiver should receive  
the same type of consideration one would give to a  
sensitive analog component.  
Agere Systems Inc.  
3

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