Datasheet > 10AX066H5F34I3SG

10AX066H5F34I3SG

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
110页	1391K
描述
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152

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10AX066H5F34I3SG 数据手册

A10-DATASHEET

2015.12.31

Transceiver Power Supply Operating Conditions

Symbol

Description

Condition

Standard POR

Fast POR

Minimum ⁽³⁾

200 µs

Typical

—

Maximum ⁽³⁾

100 ms

Unit

—

(10)(11)

t_RAMP

Power supply ramp time

200 µs

—

4 ms

Related Information

I/O Standard Specifications on page 17

Transceiver Power Supply Operating Conditions

Table 4: Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices—Preliminary

Symbol

Description

Condition ⁽¹²⁾

Chip-to-Chip ≤ 17.4 Gbps

Minimum ⁽¹³⁾

Typical

Maximum

Unit

1.0

1.03

1.06

Backplane ⁽¹⁴⁾≤ 16.0 Gbps

V_{CCT_GXB[L,R]}

Transmitter power supply

Chip-to-Chip ≤ 11.3 Gbps

0.92

0.95

0.98

Backplane ⁽¹⁴⁾≤ 10.3125 Gbps

(3)

This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the

PDN tool for the additional budget for the dynamic tolerance requirements.

(10)

This is also applicable to HPS power supply. For HPS power supply, refer to t_RAMPspecifications for standard POR when HPS_PORSEL = 0 and

t_RAMPspecifications for fast POR when HPS_PORSEL = 1.

(11)

(12)

t_rampis the ramp time of each individual power supply, not the ramp time of all combined power supplies.

These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data

rate ranges.

This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the

PDN tool for the additional budget for the dynamic tolerance requirements.

Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal

impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.

(13)

(14)

Arria 10 Device Datasheet

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