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1.5KE82ARL4

更新时间： 2024-02-27 18:41:31
品牌 Logo 应用领域
安森美 - ONSEMI 瞬态抑制器二极管局域网
页数 文件大小 规格书
7页 77K
描述
1500 Watt Mosorb TM Zener Transient Voltage Suppressors

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1.5KE82ARL4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：O-PALF-W2Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8541.10.00.50
风险等级：5.56其他特性：EXCELLENT CLAMPING CAPABILITY, UL RECOGNIZED, HIGH RELIABILITY, LOW IMPEDANCE
最大击穿电压：86.1 V最小击穿电压：77.9 V
外壳连接：ISOLATED配置：SINGLE
二极管元件材料：SILICON二极管类型：TRANS VOLTAGE SUPPRESSOR DIODE
JESD-30 代码：O-PALF-W2JESD-609代码：e3
最大非重复峰值反向功率耗散：1500 W元件数量：1
端子数量：2封装主体材料：PLASTIC/EPOXY
封装形状：ROUND封装形式：LONG FORM
峰值回流温度（摄氏度）：260极性：UNIDIRECTIONAL
最大功率耗散：5 W认证状态：Not Qualified
最大重复峰值反向电压：70.1 V表面贴装：NO
技术：ZENER端子面层：TIN
端子形式：WIRE端子位置：AXIAL
处于峰值回流温度下的最长时间：40Base Number Matches：1

1.5KE82ARL4 数据手册

 浏览型号1.5KE82ARL4的Datasheet PDF文件第1页浏览型号1.5KE82ARL4的Datasheet PDF文件第2页浏览型号1.5KE82ARL4的Datasheet PDF文件第3页浏览型号1.5KE82ARL4的Datasheet PDF文件第4页浏览型号1.5KE82ARL4的Datasheet PDF文件第6页浏览型号1.5KE82ARL4的Datasheet PDF文件第7页 
1N6267A Series  
1N6373, ICTE-5, MPTE-5,  
through  
1.5KE6.8CA  
through  
1N6389, ICTE-45, C, MPTE-45, C  
1.5KE200CA  
1000  
500  
1000  
V
ꢀ=ꢀ6.8 to 13ꢀV  
V
ꢀ=ꢀ6.8 to 13ꢀV  
20ꢀV  
BR(NOM)  
BR(NOM)  
T ꢀ=ꢀ25°C  
P
T ꢀ=ꢀ25°C  
L
t ꢀ=ꢀ10ꢀms  
P
L
t ꢀ=ꢀ10ꢀms  
500  
20ꢀV  
24ꢀV  
43ꢀV  
75ꢀV  
43ꢀV  
24ꢀV  
200  
100  
50  
200  
100  
50  
20  
20  
180ꢀV  
120ꢀV  
10  
5
10  
5
2
1
2
1
0.3  
0.5 0.7  
1
2
3
5
7
10  
20 30  
(VOLTS)  
0.3  
DV , INSTANTANEOUS INCREASE IN V ABOVE V (VOLTS)  
BR(NOM)  
0.5 0.7  
1
2
3
5
7
10  
20 30  
DV , INSTANTANEOUS INCREASE IN V ABOVE V  
BR BR  
BR(NOM)  
BR  
BR  
Figure 6. Dynamic Impedance  
1
0.7  
0.5  
0.3  
0.2  
PULSE WIDTH  
10 ms  
0.1  
0.07  
0.05  
1 ms  
0.03  
0.02  
100 ms  
10 ms  
0.01  
0.1  
0.2  
0.5  
1
2
5
10  
20  
50 100  
D, DUTY CYCLE (%)  
Figure 7. Typical Derating Factor for Duty Cycle  
APPLICATION NOTES  
RESPONSE TIME  
application, since the main purpose for adding a transient  
suppressor is to clamp voltage spikes. These devices have  
excellent response time, typically in the picosecond range  
and negligible inductance. However, external inductive  
effects could produce unacceptable overshoot. Proper  
circuit layout, minimum lead lengths and placing the  
suppressor device as close as possible to the equipment or  
components to be protected will minimize this overshoot.  
In most applications, the transient suppressor device is  
placed in parallel with the equipment or component to be  
protected. In this situation, there is a time delay associated  
with the capacitance of the device and an overshoot  
condition associated with the inductance of the device and  
the inductance of the connection method. The capacitance  
effect is of minor importance in the parallel protection  
scheme because it only produces a time delay in the  
transition from the operating voltage to the clamp voltage as  
shown in Figure 8.  
The inductive effects in the device are due to actual  
turn-on time (time required for the device to go from zero  
current to full current) and lead inductance. This inductive  
effect produces an overshoot in the voltage across the  
equipment or component being protected as shown in  
Figure 9. Minimizing this overshoot is very important in the  
Some input impedance represented by Z is essential to  
in  
prevent overstress of the protection device. This impedance  
should be as high as possible, without restricting the circuit  
operation.  
DUTY CYCLE DERATING  
The data of Figure 1 applies for non-repetitive conditions  
and at a lead temperature of 25°C. If the duty cycle increases,  
the peak power must be reduced as indicated by the curves  
of Figure 7. Average power must be derated as the lead or  
http://onsemi.com  
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