Datasheet > ZSP200

ZSP200

更新时间： 2024-10-14 03:07:43

品牌	Logo	应用领域
LSI		/
页数	文件大小	规格书
2页	60K
描述
Highly Efficient Quad-MAC DSP Core

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中文翻译

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数据手册

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ZSP200 数据手册

ZSP540 - Highly Efficient

Quad-MAC DSP Core

O V E R V I E W

C O R E F E A T U R E S

The ZSP540 processor core is a high-performance/power-efficient Quad-

MAC/Six-ALU implementation of the ZSP^®G2 architecture. The ZSP540 utilizes a

16-bit architecture with extensive 32-bit capabilities and sets an unmatched

balance of performance/power/size and memory utilization efficiency. The

Z.Turbo feature provides the SOC designer with the option to extend the ZSP540

Instruction Set and the ability to add application-specific acceleration logic.

• Quad-MAC/Six-ALU DSP core

• 4+1 instructions per cycle

• Up to 350MHz, 8-stage pipeline design

• Up to 1750 million instructions/sec

• Dual 64-bit wide Load/Store data ports

• Z.Turbo coprocessor extensions capable

• 24-bit address space

T A R G E T M A R K E T S

• 2.5/3G wireless baseband processing

• Multimedia wireless and mobile devices

• Cable/xDSL

• HW managed instructions scheduling

• HW/SW controlled power management

• Real-time trace and profiling capability

• Full AMBA/AHB support (optional)

• JTAG debug interface

• Wireless LAN (WLAN)

• Set-top box and home gateways

• Multi-channel Voice Over IP (VoIP)

• Software Defined Radio (SDR)

• Static, single phase clocked design

• Compatible with all other ZSP cores

A P P L I C A T I O N B E N E F I T S

• High-performance DSP capabilities

A R C H I T E C T U R E F E A T U R E S

• Embedded control processing efficiency

• 32-bit addressing capabilities

• Excellent power/cost/speed balance

• Excellent multimedia audio/video processing

• Power efficient baseband processing performance

• DSP and system control functions handling capabilities

• 16 and 32-bit standard instruction set

• Extensive 32-bit and 40-bit support

• Easy to program instruction set

• Load/store register based instructions

• Outstanding code density

Instruction

Sequence Unit

(ISU)

Pipeline

Control Unit

(PCU)

Prefetch Unit (PFU)

Instruction Cache

128-bit

Interrupt Control

Co-Processor IF

• User extensible instruction set

64-bit

Load/Store Unit (LSU)

Dual AGU

S U P P O R T

Debug IF

File

• Highly optimized C-compiler

• Multimedia, voice and wireless experts

• Local support by ZSP solution experts

Bypass Logic

Timers

Multiply/ALU Unit 0

Multiply/ALU Unit 1

ALU Unit

40-bit 16x16 16x16

40-bit

ALU

16x16 16x16

MAC MAC

16-bit

ALU

16-bit

ALU

MAC

中文翻译

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