Datasheet > ZR36015

ZR36015

更新时间： 2024-01-29 04:48:42

品牌	Logo	应用领域
其他 - ETC		转换器栅
页数	文件大小	规格书
27页	168K
描述
RASTER TO BLOCK CONVERTER

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技术参数
数据手册

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ZR36015 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

ZR36015 数据手册

ZR36015

PRELIMINARY

RASTER TO BLOCK CONVERTER

FEATURES

■ Real Time Raster to/from Block Conversion

■ 1/2 Decimation Processing in the Horizontal Direction

■ 30 MHz Maximum Clock Rate

■ Supports 1:0:0,4:2:2,and 4:1:1 data formats

■ 100-pin plastic quad ﬂat package (PQFP)

■ TTL level Input/Output

■ Only Image in Preset Window is Converted

■ Synchronous data and controls

■ Compatable with Zorans ZR36050 JPEG Coder and

■ Low power consumption: 0.45W (Typ.)

■ CMOS circuit operating with a single 5V power supply

ZR36011 Color Space Converter

APPLICATIONS

■ Image processing

■ Multi-media

■ Scanners

■ Image Capture

■ Image Storage

DESCRIPTION

The ZR36015 performes raster to/from block conversion for

image compression and expansion applications, and it can be

connected directly to the ZR36050 JPEG coder and the

ZR36011 Color Space Converter.

image is 16K. These numbers vary according to the mode of

operation.

The ZR36015 supports 4:0:0, 4:1:1, and 4:2:2 data formats, and

one half decimation in horizontal direction during compression.

An image compression system can be easily constructed using

the ZR36015 with the ZR35060 and ZR36011.

The maximum data transfer rate to the ZR36050 coder is 30

MHz.

The ZR36015 uses a double buffered external SRAM Strip

Buffer to support raster to/from block conversion and block inter-

leave.

[The ZR36015 is fabricated with an advanced low-power CMOS

technology, making it suitable for use in low-power, cost sensi-

tive applications. The device is availiable in a 100 pin , Plastic

Quad Flat Package (PQFP).]

The maximum number of pixels that can be processed per line

is 8K. The maximum number of lines that can be prcessed per

Host Interface

SPH WR

ADD(1:0)

Internal Register Control

MWE

MOE

Raster/Block

Address

Generator

CBSY

MADD(15:0)

Memory

Interface

PXDATA(15:0)

MWE

MOE

CBUSY

HEN

1/2

Decimation

PXDATA(15:0)

Pixel

Interface

Memory

Interface

MADD(15:0)

VEN

MDATA(15:0)

WINDOW

BSY

Pixel

MDATA(15:0)

Interface

HEN

VEN

CLKCSC

Window

Control

RESET

WINDOW

BSY

SYSCLK

SPH

Host

BDATA(7:0)

Interface

COE

EOS

CLKCSC

Coder

Interface

ADD(1:0)

Interface Logic

I/F

System

Clock

STOP

DSYNC

SYSCLK

RESET

DSYNC

STOP

EOS

BDATA(7:0)

System

Reset

COE

Coder Interface

Figure 1. ZR36015 Block Diagram

Figure 2. ZR36015 Logical Pinout

^{ZORAN Corporation}■ ^{1705 Wyatt Drive}■ ^{Santa Clara, CA 95054}■ ^{(408) 986-1314}■ ^{FAX (408) 986-1240}

June 1993

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