Driving the Digital Lifestyle
NRED-1
DVD
Digital Camera
Digital TV
Imaging
IP Cores
Noise Reduction Processor
Zoran Corporation
1390 Kifer Road
Sunnyvale, CA 94086-5305
Te l 408.523.6500
Fax 408.523.6501
www.zoran.com
Product Brief
Description
Zoran's NRED-1 Noise Reduction Processor is a silicon efficient, high
performance Intellectual Property Core for video IC designs requiring
noise reduction. NRED-1 is based on Zoran's extensive experience
delivering high quality, high volume video ICs to major consumer
products manufacturers worldwide. NRED-1 employs impulse, spatial
and temporal noise reduction techniques along with robust motion
detection to achieve the highest quality video possible in the presence
of noise. NRED-1 enables display processors to provide superior
video output and is useful for video compression systems where
reducing noise is essential for eliminating unwanted artifacts.
The NRED-1 Noise Reduction Processor greatly reduces the risk
and time involved when integrating the video noise reduction func-
tion into an IC. Expensive, discrete components can be eliminated
from system designs. When used in conjuntion with Zoran's Frame-
It-1 Deinterlacer, a silicon and memory efficient implementation can
be achieved for systems requiring progressive output.
VIP-II Demonstration System
Zoran offers the VIP-II FPGA demonstration system for evaluation of
the NRED-1 Noise Reduction Processor. The VIP-II allows cus-
tomers to input composite, s-video or component video to test
NRED-1's performance.
Features
• Impulse Noise Reduction
• Silicon efficient, fully synchronous design
• Adaptive Spatial Noise Reduction
• Motion Adaptive Temporal Noise Reduction
• Robust Motion Detection
• Requires only a single clock input ranging from 20 to 30 MHz
• Combinable with Zoran's Deinterlacers for efficient implementation
• Process technology independent "softcore"
• 3:2 and 2:2 pulldown detection
Integrated Circuit Applications
• LCD display controllers
• PDP-TV
• Digital TV
• LCD-TV
• Projector TV Systems
• Video compression systems
Deliverables
• Compilable Verilog source code
• Bit accurate, cycle accurate C++ model
• Synopsis synthesis scripts
• Test input files
• Documentation
• VIP-II demonstration system available
Figure 1. NRED-1 Noise Processor Block Diagram
NRED-1 Noise Reduction IP Core
Motion
Detector
Line
Buffers
Impulse
Noise
Reduced Noise
Video Out
Spatial
Filter
Temporal
Filter
Reduction
Filter
Field
Buffers
Input
Control
Video In
Field Buffer
Control
Output
Control
4:2:2 or 4:2:0
Noise
Detector
Film-mode Flag
Scene-cut Flag
Film-mode/
Scene-cut
Detector
7/16/04-TS
NRED-1-PB-1.0