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ZL50235 PDF预览

ZL50235

更新时间: 2024-09-24 04:23:27
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
43页 659K
描述
16 Channel Voice Echo Canceller

ZL50235 数据手册

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ZL50235  
16 Channel Voice Echo Canceller  
Data Sheet  
March 2006  
Features  
Independent multiple channels of echo  
Ordering Information  
cancellation; from 16 channels of 64 ms to 8  
channels of 128 ms with the ability to mix  
channels at 128 ms or 64 ms in any combination  
ZL50235/QCC 100 Pin LQFP Trays  
ZL50235/GDC 208 Ball PBGA Trays  
ZL50235QCG1 100 Pin LQFP* Trays, Bake & Drypack  
*Pb Free Matte Tin  
-40°C to +85°C  
Independent Power Down mode for each group of  
2 channels for power management  
Fully compliant to ITU-T G.165, G.168 (2000) and  
(2002) specifications  
+9 dB to -12 dB level adjusters (3 dB steps) at all  
signal ports  
Passed AT&T voice quality testing for carrier  
grade echo cancellers  
Compatible to ST-BUS and GCI interfaces with  
2 Mbps serial PCM data  
Offset nulling of all PCM channels  
10 MHz or 20 MHz master clock operation  
3.3 V IO pads and 1.8 V Logic core operation with  
5 V tolerant inputs  
PCM coding, µ/A-Law ITU-T G.711 or sign  
IEEE-1149.1 (JTAG) Test Access Port  
ZL50232, ZL50233, ZL50234 and ZL50235 have  
same pinouts in both LQFP and LBGA packages  
magnitude  
Per channel Fax/Modem G.164 2100 Hz or G.165  
2100 Hz phase reversal Tone Disable  
Per channel echo canceller parameters control  
Transparent data transfer and mute  
Applications  
Voice over IP network gateways  
Voice over ATM, Frame Relay  
T1/E1/J1 multichannel echo cancellation  
Wireless base stations  
Fast reconvergence on echo path changes  
Fully programmable convergence speeds  
Patented Advanced Non-Linear Processor with  
high quality subjective performance  
Echo Canceller pools  
Protection against narrow band signal divergence  
and instability in high echo environments  
DCME, satellite and multiplexer system  
V
V
V
SS  
DD1 (3.3 V)  
DD2 (1.8 V)  
ODE  
Rin  
Sin  
Rout  
Parallel  
Serial  
to  
to  
Serial  
Parallel  
Echo Canceller Pool  
Sout  
Group 0  
Group 1  
ECA/ECB  
Group 2  
ECA/ECB  
Group 3  
ECA/ECB  
MCLK  
Fsel  
ECA/ECB  
Note:  
Group 4  
ECA/ECB  
Group 5  
ECA/ECB  
Group 6  
ECA/ECB  
Group 7  
ECA/ECB  
Refer to Figure 4  
for Echo Canceller  
block diagram  
PLL  
C4i  
F0i  
RESET  
Timing  
Unit  
Microprocessor Interface  
Test Port  
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST  
Figure 1 - ZL50235 Device Overview  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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