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ZL50234/GDC PDF预览

ZL50234/GDC

更新时间: 2024-02-08 10:34:40
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信综合业务数字网电信集成电路
页数 文件大小 规格书
44页 650K
描述
ISDN Echo Canceller, 1-Func, CMOS, PBGA208, 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208

ZL50234/GDC 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:LBGA, BGA208,16X16,40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.72
JESD-30 代码:S-PBGA-B208JESD-609代码:e0
长度:17 mm功能数量:1
端子数量:208最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA208,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
峰值回流温度(摄氏度):225电源:1.8,3.3 V
认证状态:Not Qualified座面最大高度:1.5 mm
子类别:Other Telecom ICs标称供电电压:1.8 V
表面贴装:YES技术:CMOS
电信集成电路类型:ISDN ECHO CANCELLER温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

ZL50234/GDC 数据手册

 浏览型号ZL50234/GDC的Datasheet PDF文件第2页浏览型号ZL50234/GDC的Datasheet PDF文件第3页浏览型号ZL50234/GDC的Datasheet PDF文件第4页浏览型号ZL50234/GDC的Datasheet PDF文件第5页浏览型号ZL50234/GDC的Datasheet PDF文件第6页浏览型号ZL50234/GDC的Datasheet PDF文件第7页 
ZL50234  
8 Channel Voice Echo Canceller  
Data Sheet  
March 2006  
Features  
Independent multiple channels of echo  
Ordering Information  
cancellation; from 8 channels of 64 ms to 4  
channels of 128 ms with the ability to mix  
channels at 128 ms or 64 ms in any combination  
ZL50234/QCC  
ZL50234/GDC  
100 Pin LQFP Trays  
208 Ball PBGA Trays  
ZL50234QCG1 100 Pin LQFP* Trays, Bake & Drypack  
*Pb Free Matte Tin  
Independent Power Down mode for each group of  
2 channels for power management  
-40°C to +85°C  
Fully compliant to ITU-T G.165, G.168 (2000) and  
(2002) specifications  
Protection against narrow band signal divergence  
and instability in high echo environments  
+9 dB to -12 dB level adjusters (3 dB steps) at all  
signal ports  
Passed AT&T voice quality testing for carrier  
grade echo cancellers.  
Compatible to ST-BUS and GCI interfaces with  
2 Mbps serial PCM data  
Offset nulling of all PCM channels  
10 MHz or 20 MHz master clock operation  
PCM coding, µ/A-Law ITU-T G.711 or sign  
3.3 V I/O pads and 1.8 V Logic core operation with  
5 V tolerant inputs  
IEEE-1149.1 (JTAG) Test Access Port  
magnitude  
Per channel Fax/Modem G.164 2100 Hz or G.165  
2100 Hz phase reversal Tone Disable  
ZL50232, ZL50233, ZL50234 and ZL50235 have  
same pinouts in both LQFP and LBGA packages  
Per channel echo canceller parameters control  
Transparent data transfer and mute  
Fast reconvergence on echo path changes  
Fully programmable convergence speeds  
Patented Advanced Non-Linear Processor with  
high quality subjective performance  
Applications  
Voice over IP network gateways  
Voice over ATM, Frame Relay  
T1/E1/J1 multichannel echo cancellation  
V
V
SS  
V
DD1 (3.3 V)  
DD2 (1.8 V)  
ODE  
Rin  
Sin  
Rout  
Parallel  
Serial  
to  
to  
Serial  
Parallel  
Echo Canceller Pool  
Sout  
Group 0  
ECA/ECB  
Group 1  
ECA/ECB  
Group 2  
ECA/ECB  
Group 3  
ECA/ECB  
Fsel  
MCLK  
Note:  
Refer to Figure 4  
for Echo Canceller  
block diagram  
PLL  
C4i  
F0i  
RESET  
Timing  
Unit  
Microprocessor Interface  
Test Port  
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST  
Figure 1 - ZL50234 Device Overview  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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