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ZL50060GAG2 PDF预览

ZL50060GAG2

更新时间: 2024-01-03 04:28:57
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关电信集成电路电信转换电路电信电路
页数 文件大小 规格书
99页 772K
描述
16 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 64 Inputs and 64 Outputs

ZL50060GAG2 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:BGA,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.76
Is Samacsys:NJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:17 mm
功能数量:1端子数量:256
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.8 mm标称供电电压:1.8 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:17 mmBase Number Matches:1

ZL50060GAG2 数据手册

 浏览型号ZL50060GAG2的Datasheet PDF文件第2页浏览型号ZL50060GAG2的Datasheet PDF文件第3页浏览型号ZL50060GAG2的Datasheet PDF文件第4页浏览型号ZL50060GAG2的Datasheet PDF文件第5页浏览型号ZL50060GAG2的Datasheet PDF文件第6页浏览型号ZL50060GAG2的Datasheet PDF文件第7页 
ZL50060/1  
16 K-Channel Digital Switch with High Jitter  
Tolerance, Per Stream Rate Conversion (2, 4, 8,  
16, or 32 Mbps), and 64 Inputs and 64 Outputs  
Data Sheet  
February 2006  
Features  
16,384-channel x 16,384-channel non-blocking  
Ordering Information  
unidirectional switching.The Backplane and Local  
inputs and outputs can be combined to form a  
non-blocking switching matrix with 64 input  
streams and 64 output streams  
ZL50060GAC  
ZL50060GAG2  
ZL50061GAG  
ZL50061GAG2  
256 Ball PBGA  
256 Ball PBGA**  
272 Ball PBGA  
272 Ball PBGA**  
Trays  
Trays  
Trays  
Trays  
8,192-channel x 8,192-channel non-blocking  
Backplane input to Local output stream switch  
**Pb Free Tin/Silver/Copper  
-40°C to +85°C  
8,192-channel x 8,192-channel non-blocking  
Local input to Backplane output stream switch  
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any  
combination, or a fixed allocation of 16 input and  
16 output streams at 32.768 Mbps  
8,192-channel x 8,192-channel non-blocking  
Backplane input to Backplane output switch  
Exceptional input clock jitter tolerance (17 ns for  
16 Mbps or lower data rates, 14 ns for 32 Mbps)  
8,192-channel x 8,192-channel non-blocking  
Local input to Local output stream switch  
Per-stream channel and bit delay for Local and  
Backplane input streams  
Rate conversion on all data paths, Backplane-to-  
Local, Local-to-Backplane, Backplane-to-  
Backplane and Local-to-Local streams  
Per-stream advancement for Local and Backplane  
output streams  
Backplane port accepts 32 input and 32 output  
ST-BUS streams with data rates of 2.048 Mbps,  
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any  
combination, or a fixed allocation of 16 input and  
16 output streams at 32.768 Mbps  
Constant 2-frame throughput delay for frame  
integrity  
Per-channel high impedance output control for  
Local and Backplane streams  
Local port accepts 32 input and 32 output ST-  
BUS streams with data rates of 2.048 Mbps,  
V
V
V
SS (GND)  
DD_IO  
DD_CORE  
RESET  
ODE  
Backplane Data Memories  
(8,192 channels)  
BSTi0-31  
LSTi0-31  
LSTo0-31  
Backplane  
Local  
Backplane  
Interface  
Local  
Interface  
Connection Memory  
(8,192 locations)  
Connection Memory  
(8,192 locations)  
BSTo0-31  
BCST0-3  
BORS  
LCST0-3  
LORS  
Local Data Memories  
(8,192 channels)  
FP8o  
FP16o  
C8o  
Input  
Timing Unit  
Output  
Timing  
Unit  
FP8i  
C8i  
C16o  
Microprocessor Interface  
and Internal Registers  
PLL  
Test Port  
V
TMS TDi TDo TCK TRST  
D15-0  
A14-0  
DD_PLL  
DS CS R/W  
DTA  
Figure 1 - ZL50060/1 Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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