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ZL50057GAC PDF预览

ZL50057GAC

更新时间： 2024-01-14 20:03:17
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关电信集成电路电信转换电路电信电路
页数 文件大小 规格书
108页 817K
描述
12 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 48 Inputs and 48 Outputs

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ZL50057GAC 技术参数

是否Rohs认证：不符合生命周期：Transferred
包装说明：BGA, BGA272,20X20,50Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.89
Is Samacsys：NJESD-30 代码：S-PBGA-B272
JESD-609代码：e0长度：27 mm
湿度敏感等级：1功能数量：1
端子数量：272最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA272,20X20,50
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：225电源：1.8,3.3 V
认证状态：Not Qualified座面最大高度：2.54 mm
子类别：Other Telecom ICs标称供电电压：1.8 V
表面贴装：YES电信集成电路类型：DIGITAL TIME SWITCH
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：27 mmBase Number Matches：1

ZL50057GAC 数据手册

 浏览型号ZL50057GAC的Datasheet PDF文件第2页浏览型号ZL50057GAC的Datasheet PDF文件第3页浏览型号ZL50057GAC的Datasheet PDF文件第4页浏览型号ZL50057GAC的Datasheet PDF文件第5页浏览型号ZL50057GAC的Datasheet PDF文件第6页浏览型号ZL50057GAC的Datasheet PDF文件第7页 
ZL50057/8  
12 K-Channel Digital Switch with High Jitter  
Tolerance, Per Stream Rate Conversion (2, 4, 8,  
16, or 32 Mbps), and 48 Inputs and 48 Outputs  
Data Sheet  
January 2006  
Features  
•
12,288-channel x 12,288-channel non-blocking  
Ordering Information  
unidirectional switching.The Backplane and Local  
inputs and outputs can be combined to form a  
non-blocking switching matrix with 48 input  
streams and 48 output streams  
ZL50057GAC  
ZL50058GAC  
272-Ball PBGA  
256 Ball PBGA  
Trays  
Trays  
Trays  
ZL50058GAG2 256 Ball PBGA**  
**Pb Free Tin/Silver/Copper  
•
•
•
•
•
8,192-channel x 4,096-channel non-blocking  
Backplane input to Local output stream switch  
-40°C to +85°C  
4,096-channel x 8,192-channel non-blocking  
Local input to Backplane output stream switch  
8,192-channel x 8,192-channel non-blocking  
Backplane input to Backplane output switch  
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any  
combination, or a fixed allocation of 8 input and 8  
output streams at 32.768 Mbps  
•
•
Exceptional input clock jitter tolerance (17 ns for  
16 Mbps or lower data rates, 14 ns for 32 Mbps)  
4,096-channel x 4,096-channel non-blocking  
Local input to Local output stream switch  
Per-stream channel and bit delay for Local and  
Backplane input streams  
Rate conversion on all data paths, Backplane-to-  
Local, Local-to-Backplane, Backplane-to-  
Backplane and Local-to-Local streams  
Backplane port accepts 32 input and 32 output  
ST-BUS streams with data rates of 2.048 Mbps,  
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any  
combination, or a fixed allocation of 16 input and  
16 output streams at 32.768 Mbps  
•
•
•
•
Per-stream advancement for Local and  
Backplane output streams  
•
•
Constant 2-frame throughput delay for frame  
integrity  
Per-channel high impedance output control for  
Local and Backplane streams  
Local port accepts 16 input and 16 output ST-  
BUS streams with data rates of 2.048 Mbps,  
Per-channel driven-high output control for Local  
and Backplane streams  
V
V
V
SS (GND)  
DD_IO  
DD_CORE  
RESET  
ODE  
Backplane Data Memories  
(8,192 channels)  
BSTi0-31  
LSTi0-15  
LSTo0-15  
Backplane  
Connection Memory  
(8,192 locations)  
Local  
Backplane  
Interface  
Local  
Interface  
Connection Memory  
(4,096 locations)  
BSTo0-31  
BCST0-3  
BORS  
LCST0-1  
LORS  
Local Data Memories  
(4,096 channels)  
FP8o  
FP16o  
C8o  
Input  
Output  
Timing  
Unit  
FP8i  
C8i  
Timing Unit  
C16o  
Microprocessor Interface  
and Internal Registers  
PLL  
Test Port  
V
TMS TDi TDo TCK TRST  
D15-0  
A14-0  
DS CS R/W  
DD_PLL  
DTA  
Figure 1 - ZL50057/8 Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.  
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