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ZL50050GAC PDF预览

ZL50050GAC

更新时间： 2024-11-25 07:44:39
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关电信集成电路电信转换电路电信电路
页数 文件大小 规格书
94页 695K
描述
8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs

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ZL50050GAC 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：BGA, BGA196,14X14,40Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.85
Is Samacsys：NJESD-30 代码：S-PBGA-B196
JESD-609代码：e0长度：15 mm
湿度敏感等级：1功能数量：1
端子数量：196最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA196,14X14,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：225电源：1.8,3.3 V
认证状态：Not Qualified座面最大高度：1.97 mm
子类别：Other Telecom ICs标称供电电压：1.8 V
表面贴装：YES电信集成电路类型：DIGITAL TIME SWITCH
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：15 mmBase Number Matches：1

ZL50050GAC 数据手册

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ZL50050  
8 K-Channel Digital Switch with High Jitter  
Tolerance, Per Stream Rate Conversion (2, 4, 8,  
16, or 32 Mbps), and 32 Inputs and 32 Outputs  
Data Sheet  
January 2006  
Features  
Ordering Information  
•
8,192-channel x 8,192-channel non-blocking  
unidirectional switching.The Backplane and Local  
inputs and outputs can be combined to form a  
non-blocking switching matrix with 32 input  
streams and 32 output streams  
ZL50050GAC  
196 Ball PBGA  
Trays  
ZL50050GAG2 196 Ball PBGA** Trays  
*Pb Free Tin/Silver/Copper  
-40°C to +85°C  
•
•
•
•
•
4,096-channel x 4,096-channel non-blocking  
Backplane input to Local output stream switch  
4,096-channel x 4,096-channel non-blocking  
Local input to Backplane output stream switch  
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any  
combination, or a fixed allocation of 8 input and 8  
output streams at 32.768 Mbps  
Exceptional input clock jitter tolerance (17ns for  
16Mbps or lower data rates, 14ns for 32 Mbps)  
•
•
•
•
•
•
4,096-channel x 4,096-channel non-blocking  
Backplane input to Backplane output switch  
Per-stream channel and bit delay for Local and  
Backplane input streams  
Per-stream advancement for Local and Backplane  
output streams  
4,096-channel x 4,096-channel non-blocking  
Local input to Local output stream switch  
Rate conversion on all data paths, Backplane-to-  
Local, Local-to-Backplane, Backplane-to-  
Backplane and Local-to-Local streams  
Constant 2-frame throughput delay for frame  
integrity  
•
•
Backplane port accepts 16 input and 16 output  
ST-BUS streams with data rates of 2.048 Mbps,  
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any  
combination, or a fixed allocation of 8 input and 8  
output streams at 32.768 Mbps  
Per-channel high impedance output control for  
Local and Backplane streams  
Per-channel driven-high output control for Local  
and Backplane streams  
Local port accepts 16 input and 16 output ST-  
BUS streams with data rates of 2.048 Mbps,  
V
V
V
SS (GND)  
DD_IO  
DD_CORE  
RESET  
ODE  
Backplane Data Memories  
(4,096 channels)  
BSTi0-15  
LSTi0-15  
LSTo0-15  
Backplane  
Connection Memory  
(4,096 locations)  
Local  
Backplane  
Interface  
Local  
Interface  
Connection Memory  
(4,096 locations)  
BSTo0-15  
BCST0-1  
BORS  
LCST0-1  
LORS  
Local Data Memories  
(4,096 channels)  
FP8o  
FP16o  
C8o  
Input  
Output  
Timing  
Unit  
FP8i  
C8i  
Timing Unit  
C16o  
Microprocessor Interface  
and Internal Registers  
PLL  
Test Port  
V
TMS TDi TDo TCK TRST  
D15-0  
A14-0  
DS CS R/W  
DD_PLL  
DTA  
Figure 1 - ZL50050 Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.  
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