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ZL50031 PDF预览

ZL50031

更新时间: 2022-12-08 22:47:07
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关
页数 文件大小 规格书
74页 760K
描述
Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch

ZL50031 数据手册

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ZL50031  
Flexible 4 K x 2 K Channel Digital Switch  
with H.110 Interface and  
2 K x 2 K Local Switch  
Data Sheet  
February 2005  
Features  
4,096 x 2,048 blocking switching between  
Ordering Information  
backplane and local streams  
2,048 x 2,048 non-blocking switching between  
local streams  
2,048 x 2,048 non-blocking switching between  
backplane streams  
ZL50031QEG1 256 Pin HQFP*  
*Pb Free Matte Tin  
-40°C to +85°C  
Connection memory block-programming for fast  
device initialization  
Rate conversion between backplane and local  
streams  
Pseudo-Random Binary Sequence (PRBS) pattern  
generation and testing for backplane and local  
streams  
Backplane interface accepts data rates of  
8.192 Mbps or 16.384 Mbps  
Local interface accepts data rates of 2.048 Mbps,  
4.096 Mbps or 8.192 Mbps on a per group basis  
Conforms to the mandatory requirements of the  
IEEE-1149.1 (JTAG) standard  
3.3 V operation with 5 V tolerant inputs and I/O’s  
5 V tolerant PCI driver on CT-Bus I/O’s  
Meets all the key H.110 mandatory signal  
requirements including timing  
Per-channel variable or constant throughput  
delay  
Applications  
Per-stream input delay, programmable for local  
streams on a per bit basis  
Carrier-grade VoIP Gateways  
IP-PBX and PABX  
Intregrated Access Devices  
Access Servers  
CTI Applications/CompactPCI® Platforms  
Per-stream output advancement, programmable  
for backplane and local streams  
Per-channel direction control for backplane  
streams  
Per-channel message mode for backplane and  
local streams  
H.110, H.100, ST-BUS and proprietary Backplane  
Applications  
Per-channel high impedance output control for  
backplane and local streams  
Compatible to Stratum 4 Enhanced clock  
switching standard  
Description  
The ZL50031 Digital Switch provides switching  
capacities of 4,096 x 2,048 channels between  
backplane and local streams, 2,048 x 2,048 channels  
among local streams and 2,048 x 2,048 channels  
among backplane streams. The local connected serial  
inputs and outputs have 32, 64 and 128 64 kbps  
channels per frame with data rates of 2.048, 4.096 and  
8.192 Mbps respectively. The backplane connected  
serial inputs and outputs have 128 and 256 64 kbps  
channels per frame with data rates of 8.192 and  
16.384 Mbps respectively.  
Integrated PLL conforms to Telcordia GR-1244-  
CORE Stratum 4 Enhanced switching standard  
-
Holdover Mode with holdover frequency stability  
of 0.07 ppm  
-
-
-
Jitter attenuation from 1.52 Hz  
Time interval error (TIE) correction  
Master and Slave mode operation  
Non-multiplexed microprocessor interface  
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,  
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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