ZL50012
Flexible 512-ch Digital Switch
Data Sheet
April 2006
Features
•
•
•
•
512 channel x 512 channel non-blocking switch at
2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation
Ordering Information
ZL50012/QCC 160 Pin LQFP
Trays
ZL50012/GDC 144 Ball LBGA Trays
Rate conversion between the ST-BUS inputs and
ST-BUS outputs
ZL50012QCG1 160 Ball LQFP* Trays, Bake & Drypack
ZL50012GDG2 144 Ball LBGA** Trays, Bake & Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
Per-stream ST-BUS input with data rate selection
of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
-40°C to +85°C
Per-stream ST-BUS output with data rate
selection of 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s; the output data rate can be different
than the input data rate
•
•
•
Per-channel high impedance output control
Per-channel message mode
Per-channel pseudo random bit sequence
(PRBS) pattern generation and bit error detection
•
Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
•
•
Control interface compatible to Motorola non-
multiplexed CPUs
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•
•
•
Per-stream input channel and input bit delay
programming with fractional bit delay
Connection memory block programming
capability
Per-stream output channel and output bit delay
programming with fractional bit advancement
•
•
IEEE-1149.1 (JTAG) test port
3.3V I/O with 5 V tolerant input
Multiple frame pulse outputs and reference clock
outputs
Per-channel constant throughput delay
V
V
SS
DD
RESET
ODE
STo0-15
STi0-15
S/P Converter
Input Timing
Data Memory
P/S Converter
Output HiZ Control
STOHZ0-15
FPi
CKi
Connection Memory
Microprocessor
FPo0
CKo0
FPo1
Output Timing
Test Port
Interface
and
Internal
CKo1
FPo2
Registers
CKo2
APLL
IC0 - 4
CLKBYPS
ICONN0 - 2
Figure 1 - ZL50012 Functional Block Diagram
1
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