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ZL50011 PDF预览

ZL50011

更新时间: 2024-10-30 03:08:31
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
83页 762K
描述
Flexible 512 Channel DX with on-chip DPLL

ZL50011 数据手册

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ZL50011  
Flexible 512 Channel DX with on-chip  
DPLL  
Data Sheet  
July 2005  
Features  
512 channel x 512 channel non-blocking switch at  
Ordering Information  
2.048 Mbps, 4.096 Mbps or 8.192 Mbps  
operation  
ZL50011/QCC  
160 Pin LQFP  
Rate conversion between the ST-BUS inputs and  
ZL50011/GDC 144 Ball LBGA  
ST-BUS outputs  
Integrated Digital Phase-Locked Loop (DPLL)  
meets Telcordia GR-1244-CORE Stratum 4  
specifications  
Per-stream output channel and output bit delay  
programming with fractional bit advancement  
Multiple frame pulse outputs and reference clock  
DPLL provides reference monitor, jitter  
attenuation and free run functions  
outputs  
Per-stream ST-BUS input with data rate selection  
of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps  
Per-stream ST-BUS output with data rate  
selection of 2.048 Mbps, 4.096 Mbps or  
8.192 Mbps; the output data rate can be different  
than the input data rate  
Per-stream high impedance control output for  
every ST-BUS output with fractional bit  
advancement  
Per-channel constant throughput delay  
Per-channel high impedance output control  
Per-channel message mode  
Per-channel Pseudo Random Bit Sequence  
(PRBS) pattern generation and bit error detection  
Control interface compatible to Motorola non-  
multiplexed CPUs  
Per-stream input channel and input bit delay  
Connection memory block programming capability  
IEEE-1149.1 (JTAG) test port  
3.3 V I/O with 5 V tolerant input  
programming with fractional bit delay  
V
V
SS  
DD  
RESET  
ODE  
STo0-15  
STi0-15  
S/P Converter  
Input Timing  
Data Memory  
P/S Converter  
Output HiZ Control  
FPi  
CKi  
STOHZ0-15  
Connection Memory  
FPo0  
CKo0  
FPo1  
CKo1  
FPo2  
Microprocessor  
Output Timing  
Test Port  
Interface  
REF  
DPLL  
and  
Internal  
Registers  
CKo2  
IC0 - 4  
OSC  
CLKBYPS  
ICONN1  
APLL  
Figure 1 - ZL50011 Functional Block Diagram  
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,  
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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