Datasheet > ZL50010_06

ZL50010_06

更新时间： 2024-10-14 03:08:31

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
87页	722K
描述
Flexible 512 Channel DX with Enhanced DPLL

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ZL50010_06 数据手册

ZL50010

Flexible 512 Channel DX with Enhanced

DPLL

Data Sheet

April 2006

Features

•

512 channel x 512 channel non-blocking switch

Ordering Information

at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps

operation

Rate conversion between the ST-BUS inputs and

ST-BUS outputs

Integrated Digital Phase-Locked Loop (DPLL)

meets Telcordia GR-1244-CORE Stratum 4

enhanced specifications

DPLL provides automatic reference switching,

jitter attenuation, holdover and free run functions

Per-stream ST-BUS input with data rate selection

of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps

Per-stream ST-BUS output with data rate

selection of 2.048 Mbps, 4.096 Mbps or

8.192 Mbps; the output data rate can be different

than the input data rate

ZL50010/QCC 160 Pin LQFP

Trays

ZL50010/GDC 144 Ball LBGA Trays

ZL50010QCG1 160 Pin LQFP* Trays, Bake & Drypack

ZL50010GDG2 144 Ball LBGA** Trays, Bake & Drypack

*Pb Free Matte Tin

•

**Pb Free Tin/Silver/Coppoer

-40°C to +85°C

•

Per-stream output channel and output bit delay

programming with fractional bit advancement

Multiple frame pulse outputs and reference clock

outputs

Per-channel constant throughput delay

Per-channel high impedance output control

Per-channel message mode

•

Per-channel Pseudo Random Bit Sequence

(PRBS) pattern generation and bit error detection

•

Per-stream high impedance control output for

every ST-BUS output with fractional bit

advancement

Per-stream input channel and input bit delay

programming with fractional bit delay

•

Control interface compatible to Motorola non-

multiplexed CPUs

Connection memory block programming

capability

IEEE-1149.1 (JTAG) test port

3.3 V I/O with 5 V tolerant input

•

RESET

ODE

STo0-15

STi0-15

S/P Converter

Input Timing

Data Memory

P/S Converter

Output HiZ Control

FPi

CKi

STOHZ0-15

Connection Memory

FPo0

CKo0

FPo1

PRI_REF

SEC_REF

Microprocessor

Output Timing

Test Port

Interface

and

Internal

DPLL

CKo1

FPo2

Registers

CKo2

IC0 - 4

CLKBYPS

OSC

APLL

Figure 1 - ZL50010 Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...87

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与ZL50010_06相关器件

型号	品牌	获取价格	描述	数据表
ZL50010GDC	ZARLINK	获取价格	Flexible 512 Channel DX with Enhanced DPLL
ZL50010GDG2	ZARLINK	获取价格	Flexible 512 Channel DX with Enhanced DPLL
ZL50010QCC	ZARLINK	获取价格	Flexible 512 Channel DX with Enhanced DPLL
ZL50010QCG1	ZARLINK	获取价格	Flexible 512 Channel DX with Enhanced DPLL
ZL50011	ZARLINK	获取价格	Flexible 512 Channel DX with on-chip DPLL
ZL50011/GDC	ZARLINK	获取价格	Flexible 512 Channel DX with on-chip DPLL
ZL50011/QCC	ZARLINK	获取价格	Flexible 512 Channel DX with on-chip DPLL
ZL50011_06	ZARLINK	获取价格	Flexible 512 Channel DX with on-chip DPLL
ZL50011GDC	ZARLINK	获取价格	Flexible 512 Channel DX with on-chip DPLL
ZL50011GDG2	ZARLINK	获取价格	Flexible 512 Channel DX with on-chip DPLL

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