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ZL49020 PDF预览

ZL49020

更新时间: 2024-11-30 22:34:27
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
14页 356K
描述
Wide Dynamic Range DTMF Receiver

ZL49020 数据手册

 浏览型号ZL49020的Datasheet PDF文件第2页浏览型号ZL49020的Datasheet PDF文件第3页浏览型号ZL49020的Datasheet PDF文件第4页浏览型号ZL49020的Datasheet PDF文件第5页浏览型号ZL49020的Datasheet PDF文件第6页浏览型号ZL49020的Datasheet PDF文件第7页 
ZL49010/1, ZL49020/1, ZL49030/1  
Wide Dynamic Range DTMF Receiver  
Data Sheet  
September 2003  
Features  
Wide dynamic range (50dB) DTMF Receiver  
Call progress (CP) detection via cadence  
indication  
Ordering Information  
ZL49010DAA  
ZL49011DAA  
ZL49020DAA  
ZL49021DAA  
ZL49030DCA  
ZL49030DCB  
ZL49030DDA  
ZL49030DDB  
ZL49031DCA  
ZL49031DCB  
ZL49031DDA  
ZL49031DDB  
8 Pin PDIP  
8 Pin PDIP  
8 Pin PDIP  
8 Pin PDIP  
18 Pin SOIC Tubes  
18 Pin SOIC Tape & Reel  
20 Pin SSOP Tubes  
20 Pin SSOP Tape & Reel  
18 Pin SOIC Tubes  
18 Pin SOIC Tape & Reel  
20 Pin SSOP Tubes  
Tubes  
Tubes  
Tubes  
Tubes  
4-bit synchronous serial data output  
Software controlled guard time for ZL490x0  
Internal guard time circuitry for ZL490x1  
Powerdown option (ZL4901x & ZL4903x)  
3.579MHz crystal or ceramic resonator (ZL4903x  
and ZL4902x)  
External clock input (ZL4901x)  
Guarantees non-detection of spurious tones  
Applications  
20 Pin SSOP Tape & Reel  
Integrated telephone answering machine  
End-to-end signalling  
Fax Machines  
-40°C to +85°C  
signal and requires external software guard time to  
validate the DTMF digit. The ZL490x1, with preset  
internal guard times, uses a delay steering (DStD)  
logic output to indicate the detection of a valid DTMF  
digit. The 4-bit DTMF binary digit can be clocked out  
synchronously at the serial data (SD) output. The SD  
pin is multiplexed with call progress detector output. In  
the presence of supervisory tones, the call progress  
Description  
The ZL490xx is a family of high performance DTMF  
receivers which decode all 16 tone pairs into a 4-bit  
binary code. These devices incorporate an AGC for  
wide dynamic range and are suitable for end-to-end  
signalling. The ZL490x0 provides an early steering  
(ESt) logic output to indicate the detection of a DTMF  
1
PWDN  
Steering  
Digital  
Circuit  
ESt  
or  
DStD  
VDD  
Guard  
Voltage  
Bias Circuit  
3
Time  
High  
Group  
Filter  
VSS  
Parallel to  
Serial  
Converter  
& Latch  
ACK  
Dial  
Tone  
Filter  
Anti-  
alias  
Filter  
Code  
Converter  
and  
Digital  
AGC  
Detector  
Algorithm  
Latch  
Low  
Group  
Filter  
Mux  
SD  
2
Oscillator  
OSC2  
and  
Clock  
Circuit  
Energy  
Detection  
OSC1  
(CLK)  
To All Chip Clocks  
1. ZL49010/1 and ZL49030/1 only.  
2. ZL49020/1 and ZL49030/1 only.  
3. ZL490x1 only.  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.  

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