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ZL40241 PDF预览

ZL40241

更新时间: 2024-11-30 14:55:35
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
23页 646K
描述
The ZL40241 is a pin controlled low additive jitter, low power 3 x 10 LVCMOS fanout buffer. Two in

ZL40241 数据手册

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Data Sheet  
ZL40241  
Ten LVCMOS Output Low Additive Jitter Fanout Buffer  
Ordering Information  
Features  
ZL40241LDG1  
ZL40241LDF1  
32 Pin QFN  
32 pin QFN  
Trays  
Tape and Reel  
3 to 1 input Multiplexer: Two inputs accept any  
differential (LVPECL, HCSL, LVDS, SSTL, CML,  
LVCMOS) or a single ended signal and the third  
input accepts a crystal or a single ended signal  
Package size: 5 x 5 mm  
-40 C to +85 C  
Ten 1.5V/1.8V/2.5V/3.3V LVCMOS outputs  
Supports frequencies from 0 to 200MHz  
Supports crystals from 8MHz to 60MHz  
Ultra-low additive jitter: 17fs (12kHz to 20MHz)  
Ultra-low noise floor of -170dBc/Hz  
Applications  
General purpose clock distribution  
Low jitter clock trees  
Logic translation  
Clock and data signal restoration  
Wired and Wireless communications  
High performance microprocessor clock distribution  
Medical Imaging  
Supports 2.5V or 3.3V power supplies  
Output to output skew of 30ps (typical)  
Input to output delay of 2ns (typical)  
Test equipment  
ZL40241  
OUT0  
Synchronous OE  
OE  
OUT1  
OUT2  
OUT3  
OUT4  
OUT5  
OUT6  
OUT7  
OUT8  
OUT9  
SEL0  
SEL1  
IN0_p  
IN0_n  
00  
IN1_p  
IN1_n  
01  
10  
11  
XOUT  
XIN  
Figure 1. Functional Block Diagram  
ZL40241  
October 2018  
1
© 2018 Microsemi Corporation  
 
 

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