Datasheet > ZL40234

ZL40234

更新时间： 2024-11-30 14:55:39

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
35页	1761K
描述
The ZL40234 is a pin configurable low additive jitter, low power 3 x 4 LVPECL/HCSL/LVDS fanout buf

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ZL40234 数据手册

Data Sheet

ZL40234

Low Skew, Low Additive Jitter, 4 Output LVPECL/LVDS/HCSL

Fanout Buffer with one LVCMOS output

Ordering Information

Features

ZL40234LDG1

ZL40234LDF1

32 pin QFN

Trays

Tape and Reel

• 3 to 1 input Multiplexer: Two inputs accept any

differential (LVPECL, HCSL, LVDS, SSTL, CML,

LVCMOS) or a single ended signal and the third

input accepts a crystal or a single ended signal

Package size: 5 x 5 mm



-40 C to +85 C

• Four differential LVPECL/LVDS/HCSL outputs

• One LVCMOS output

Applications

•

General purpose clock distribution

Low jitter clock trees

• Ultra-low additive jitter: 24fs (in 12kHz to 20MHz

integration band at 625MHz clock frequency)

Logic translation

• Supports clock frequencies from 0 to 1.6GHz

Clock and data signal restoration

• Supports 2.5V or 3.3V power supplies for LVPECL,

LVDS or HCSL outputs

Wired communications: OTN, SONET/SDH, GE, 10 GE,

FC and 10G FC

• Supports 1.5V, 1.8V, 2.5V or 3.3V for LVCMOS

•

PCI Express generation 1/2/3/4 clock distribution

Wireless communications

output

• Embedded Low Drop Out (LDO) Voltage regulator

provides superior Power Supply Noise Rejection

High performance microprocessor clock distribution

Test Equipment

• Maximum output to output skew of 40ps

• Device controlled via control pins

OUT_TYPE_SEL0

OUT_TYPE_SEL1

OUT_TYPE_SEL[1:0] OUTPUTs

LVECL

LVDS

OUT0_p

OUT0_n

IN_SEL0

IN_SEL1

HCSL

HIGH-Z

OUT1_p

OUT1_n

IN0_p

IN0_n

IN1_p

IN1_n

OUT2_p

OUT2_n

ZL40234

OUT3_p

OUT3_n

XOUT

XIN

OUT_LVCMOS

Synchronous

LVCMOS_OE

Figure 1. Functional Block Diagram

ZL40234

September 2018

12 3 4 5 6 7...35

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