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ZL40231 PDF预览

ZL40231

更新时间: 2024-11-30 14:55:43
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
36页 1756K
描述
The ZL40231 is a low additive jitter, low power 3 x 10 LVPECL/HCSL/LVDS fanout buffer. Two inputs

ZL40231 数据手册

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Data Sheet  
ZL40231  
Low Skew, Low Additive Jitter, 10 output LVPECL/LVDS/HCSL  
Fanout Buffer with one LVCMOS output  
Ordering Information  
Features  
ZL40231LDG1  
ZL40231LDF1  
48 Pin QFN  
48 pin QFN  
Trays  
Tape and Reel  
3 to 1 input Multiplexer: Two inputs accept any  
differential (LVPECL, HCSL, LVDS, SSTL, CML,  
LVCMOS) or a single ended signal and the third  
input accepts a crystal or a single ended signal  
Package size: 7 x 7 mm  
-40 C to +85 C  
Ten differential LVPECL/LVDS/HCSL outputs  
One LVCMOS output  
Applications  
General purpose clock distribution  
Low jitter clock trees  
Ultra-low additive jitter: 24fs (integration band:  
12kHz to 20MHz at 625MHz clock frequency)  
Logic translation  
Supports clock frequencies from 0 to 1.6GHz  
Clock and data signal restoration  
Supports 2.5V or 3.3V power supplies on LVPECL,  
Wired communications: OTN, SONET/SDH, GE, 10 GE,  
FC and 10G FC  
LVDS or HCSL outputs  
Supports 1.5V, 1.8V, 2.5V or 3.3V on LVCMOS  
PCI Express generation 1/2/3/4 clock distribution  
Wireless communications  
outputs  
Embedded Low Drop Out (LDO) Voltage regulator  
provides superior Power Supply Noise Rejection  
High performance microprocessor clock distribution  
Test Equipment  
Maximum output to output skew of 40ps  
Device controlled via control pins  
OUTA_TYPE_SEL0  
OUTA_TYPE_SEL1  
Bank A  
OUT_A_TYPE_SEL[1:0] BANK A OUTPUT  
OUT0_p  
OUT0_n  
00  
01  
10  
11  
LVECL  
LVDS  
HCSL  
HIGH-Z  
OUT1_p  
OUT1_n  
IN_SEL0  
IN_SEL1  
OUT2_p  
OUT2_n  
IN0_p  
IN0_n  
OUT3_p  
OUT3_n  
IN1_p  
IN1_n  
OUT4_p  
OUT4_n  
Bank  
B
OUT5_p  
OUT5_n  
ZL40231  
XOUT  
XIN  
OUT6_p  
OUT6_n  
OUT7_p  
OUT7_n  
OUT8_p  
OUT8_n  
OUT_B_TYPE_SEL[1:0] BANK B OUTPUT  
00  
01  
10  
11  
LVECL  
LVDS  
HCSL  
OUT9_p  
OUT9_n  
HIGH-Z  
OUTB_TYPE_SEL0  
OUTB_TYPE_SEL1  
Synchronous  
OE  
OUT10  
LVCMOS_OE  
Figure 1. Functional Block Diagram  
ZL40231  
October 2018  
1
© 2018 Microsemi Corporation  
 
 
 

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