Datasheet > ZL40230

ZL40230

更新时间： 2023-12-06 20:03:43

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
51页	1929K
描述
The ZL40230 is a programmable or hardware pin controlled low additive jitter, low power 3 x 10 LVP

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ZL40230 数据手册

Data Sheet

ZL40230

Low Skew, Low Additive Jitter 10 output LVPECL/LVDS/HCSL

Fanout Buffer with one LVCMOS output

Features

Ordering Information

• 3 to 1 input Multiplexer: Two inputs accept any

differential (LVPECL, HCSL, LVDS, SSTL, CML,

LVCMOS) or a single ended signal and the third

input accepts a crystal or a single ended signal

ZL40230LDG1

ZL40230LDF1

48 Pin QFN

48 pin QFN

Trays

Tape and Reel

Package size: 7 x 7 mm



-40 C to +85 C

• Ten differential LVPECL/LVDS/HCSL outputs

• One LVCMOS output

Applications

•

General purpose clock distribution

Low jitter clock trees

• Ultra-low additive jitter: 24fs (integration band:

12kHz to 20MHz at 625MHz clock frequency)

Logic translation

• Supports clock frequencies from 0 to 1.6GHz

Clock and data signal restoration

• Supports 2.5V or 3.3V power supplies on

Wired communications: OTN, SONET/SDH, GE, 10 GE,

FC and 10G FC

LVPECL/LVDS/HCSL outputs

• Supports 1.5V, 1.8V, 2.5V or 3.3V on LVCMOS

•

PCI Express generation 1/2/3/4 clock distribution

Wireless communications

output

• Embedded Low Drop Out (LDO) Voltage regulator

High performance microprocessor clock distribution

Test Equipment

provides superior Power Supply Noise Rejection

• Maximum output to output skew of 40ps

• Device controlled via SPI or hardware control pins

SEL

SPI Slave

Bank A

Registers:

LVCMOS_OE/

SPI_CS_b

xtal_buf_gain[7:0]

xtal_drive_level[7:0]

xtal_load_cap[7:0]

input_select[1:0]

OUT0_p

OUT0_n

output_drive_low

IN_SEL0

SPI_CLK

IN_SEL0/

SPI_CLK

driver_type[7:0] (diff)

driver_type[9:8] (diff)

driver_type[17:10] (diff)

driver_type[19:18] (diff)

cmos_div[2:0] (cmos)

output_enable (cmos)

driver_strength (cmos)

Device ID

OUT1_p

OUT1_n

IN_SEL1/

SPI_SDI

IN_SEL1

SPI_SDIO

OUT2_p

OUT2_n

OUTB_TYPE_SEL0/

SPI_SDO

OUTB_TYPE_SEL1

OUTA_TYPE_SEL0

OUTA_TYPE_SEL1

OUT3_p

OUT3_n

OUT4_p

OUT4_n

IN0_p

IN0_n

Bank

OUT5_p

OUT5_n

IN1_p

IN1_n

OUT6_p

OUT6_n

OUT7_p

OUT7_n

XOUT

XIN

OUT8_p

OUT8_n

ZL40230

OUT9_p

OUT9_n

DIV

1to8

OUT10

Figure 1. Functional Block Diagram

ZL40230

October 2018

12 3 4 5 6 7...51

下载PDF

与ZL40230相关器件

型号	品牌	描述	获取价格	数据表
ZL40231	MICROCHIP	The ZL40231 is a low additive jitter, low power 3 x 10 LVPECL/HCSL/LVDS fanout buffer. Tw	获取价格
ZL40234	MICROCHIP	The ZL40234 is a pin configurable low additive jitter, low power 3 x 4 LVPECL/HCSL/LVDS fa	获取价格
ZL40235	MICROCHIP	The ZL40235 is a programmable or hardware pin controlled low additive jitter, low power 3	获取价格
ZL40235LDG1	MICROCHIP	Clock Driver	获取价格
ZL40240	MICROCHIP	The ZL40240 is a programmable or hardware pin controlled low additive jitter, low power 3	获取价格
ZL40241	MICROCHIP	The ZL40241 is a pin controlled low additive jitter, low power 3 x 10 LVCMOS fanout buffer	获取价格