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ZL40211 PDF预览

ZL40211

更新时间: 2024-11-30 14:53:51
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
26页 594K
描述
The ZL40211 is an LVPECL clock fan out buffer with two input and eight output clock drivers capabl

ZL40211 数据手册

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ZL40211  
Precision 2:8 LVPECL Fanout Buffer with Glitch-  
free Input Reference Switching and On-Chip  
Input Termination  
Data Sheet  
April 2014  
Features  
Ordering Information  
ZL40211LDG1  
ZL40211LDF1  
32 Pin QFN  
32 Pin QFN  
Trays  
Tape and Reel  
Inputs/Outputs  
Accepts two differential or single-ended inputs  
Matte Tin  
LVPECL, LVDS, CML, HCSL, LVCMOS  
Package size: 5 x 5 mm  
-40oC to +85oC  
Glitch-free switching of references  
On-chip input termination resistors and biasing for  
AC coupled inputs  
Applications  
General purpose clock distribution  
Low jitter clock trees  
Eight precision LVPECL outputs  
Operating frequency up to 750 MHz  
Logic translation  
Power  
Clock and data signal restoration  
Redundant clock distribution  
Options for 2.5 V or 3.3 V power supply  
Core current consumption of 122 mA  
Wired communications: OTN, SONET/SDH, GE,  
10 GE, FC and 10G FC  
On-chip Low Drop Out (LDO) Regulator for superior  
power supply rejection  
PCI Express generation 1/2/3 clock distribution  
Wireless communications  
Performance  
Ultra low additive jitter of 106 fs RMS  
High performance microprocessor clock  
distribution  
out0_p  
out0_n  
out1_p  
out1_n  
ctrl0  
vt0  
Termination  
and Bias  
out2_p  
out2_n  
clk0_p  
clk0_n  
out3_p  
out3_n  
clk1_p  
clk1_n  
Buffer  
out4_p  
out4_n  
ctrl1  
vt1  
Termination  
and Bias  
out5_p  
out5_n  
out6_p  
out6_n  
sel  
out7_p  
out7_n  
Figure 1 - Functional Block Diagram  
1
Microsemi Corporation  
Copyright 2014, Microsemi Corporation. All Rights Reserved.  

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