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ZL40209 PDF预览

ZL40209

更新时间: 2024-11-30 14:55:03
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
26页 597K
描述
The ZL40209 is an LVPECL clock fan out buffer with two input and six output clock drivers capable

ZL40209 数据手册

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ZL40209  
Precision 2:6 LVPECL Fanout Buffer with Glitch-  
free Input Reference Switching and On-Chip  
Input Termination  
Data Sheet  
April 2014  
Features  
Ordering Information  
ZL40209LDG1 32 Pin QFN  
Trays  
Inputs/Outputs  
ZL40209LDF1  
32 Pin QFN  
Tape and Reel  
Accepts two differential or single-ended inputs  
Matte Tin  
LVPECL, LVDS, CML, HCSL, LVCMOS  
Package size: 5 x 5 mm  
-40oC to +85oC  
Glitch-free switching of references  
On-chip input termination resistors and biasing for  
AC coupled inputs  
Applications  
Six precision LVPECL outputs  
General purpose lock distribution  
Low jitter clock trees  
Operating frequency up to 750 MHz  
Power  
Logic translation  
Options for 2.5 V or 3.3 V power supply  
Clock and data signal restoration  
Redundant clock distribution  
Core current consumption of 110 mA  
On-chip Low Drop Out (LDO) Regulator for superior  
power supply rejection  
Wired communications: OTN, SONET/SDH, GE,  
10 GE, FC and 10G FC  
Performance  
PCI Express generation 1/2/3 clock distribution  
Wireless communications  
Ultra low additive jitter of 106 fs RMS  
High performance microprocessor clock  
distribution  
out0_p  
out0_n  
ctrl0  
vt0  
Termination  
and Bias  
out1_p  
out1_n  
clk0_p  
clk0_n  
out2_p  
out2_n  
clk1_p  
clk1_n  
Buffer  
out3_p  
out3_n  
ctrl1  
vt1  
Termination  
and Bias  
out4_p  
out4_n  
out5_p  
out5_n  
sel  
Figure 1 - Functional Block Diagram  
1
Microsemi Corporation  
Copyright 2014, Microsemi Corporation. All Rights Reserved.  

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