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ZL38015 PDF预览

ZL38015

更新时间: 2024-09-13 03:08:35
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
3页 134K
描述
Voice Processor

ZL38015 数据手册

 浏览型号ZL38015的Datasheet PDF文件第2页浏览型号ZL38015的Datasheet PDF文件第3页 
ZL38015  
Voice Processor  
Data Sheet  
A full Design Manual is available to qualified  
customers. To register, please send an email to  
VoiceProcessing@Zarlink.com.  
June 2007  
Ordering Information  
ZL38015QCG1  
100 Pin LQFP  
Trays, Bake &  
Drypack  
Features  
*Pb Free Matte Tin  
100 MHz (200 MIPs) Zarlink voice processor with  
Butterfly hardware accelerator and  
breakpoint/interrupt controller  
-40°C to +85°C  
On-board Data (26 Kbytes), Instruction (24  
Kbytes RAM and Boot (3 Kbytes) ROM  
1.2 V Core; 3.3 V IO with 5 V-tolerant inputs  
IEEE-1149.1 compatible JTAG port  
2048 tap Filter co-processor shared across up to  
16 separate functions in 128 tap increments  
Applications  
Primary PCM port supports TDM (ST BUS, GCI or  
McBSP framing) or SSI modes at bit rates of 128,  
256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec  
Wireless Local Loop base stations and controllers  
Voice telephony gateways  
Separate slave (microcontroller) and master  
Digital, VoIP based and wireless PBX systems  
Echo Canceller pools  
(Flash) SPI ports, maximum clock rate = 25 MHz  
Watchdog and 2 auxiliary timers  
Customer Premise equipment  
Integrated access devices  
SOHO gateways  
11 General Purpose Input/Output (GPIO) pins  
General purpose UART port  
Bootloadable for future Zarlink software upgrades  
External oscillator or crystal/ceramic resonator  
OSCo  
IRQ[15:0]  
100 MHz MCLK  
APLL  
OSC  
Instruction  
Interrupt  
OSCi  
PCM_CLKi  
PCM_LBCi  
RAM  
Controller  
PCM P0  
24 K  
Clock  
DSP  
Bytes  
5
/
JTAG  
Core  
Chain  
Boot  
ROM  
3 K  
Timing  
Bytes  
Generator  
Device Clocks  
IRQ  
Data RAM  
5
/
IRQ  
Master  
SPI  
IRQ  
5
/
27 K  
ButterFly  
Hardware  
Accelerator  
Bytes  
PCM P0  
4
/
IRQ  
Slave  
SPI  
IRQ  
2
/
IRQ  
Watchdog  
APLL  
IRQ  
IRQ  
UART  
GPIO  
IRQ  
IRQ  
5
AUX Timer1  
AUX Timer2  
Filter  
11  
/
/
PCM P1  
MCLK  
Co-processor  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.  

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