Datasheet > ZL38012LDF1

ZL38012LDF1

更新时间： 2024-11-19 18:59:55

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
7页	90K
描述
Consumer IC

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中文翻译

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技术参数
数据手册

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ZL38012LDF1 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.83
Base Number Matches：	1

ZL38012LDF1 数据手册

ZL38012

Voice Processor with

Dual Narrow Band Codecs

Data Sheet

September 2010

A full Design Manual is available to qualified

customers. To register, please send an email to

VoiceProcessing@Zarlink.com.

Ordering Information

ZL38012LDG1

56 Pin QFN*

*Pb Free Matte Tin

Features

-40C to +85C

•

100 MHz (200 MIPs) Zarlink voice processor with

hardware accelerator.

•

Bootloadable for future Zarlink software upgrades

External oscillator or crystal/ceramic resonator

1.2 V Core; 3.3 V IO with 5 V-tolerant inputs

•

Dual 8 kHz sampling  ADCs with input buffer

gain selection

•

Dual 8 kHz DACs with internal output driver

Dual function Inter-IC Sound (I²S) port or TDM

Port

Applications

•

Hands-free car kits

•

PCM port supports TDM (ST BUS, GCI or McBSP

framing) or SSI modes at bit rates of 128, 256, 512,

1024, 2048, 4096, 8192 or 16384 Kb/sec

Full duplex speaker-phone for digital telephone

Echo cancellation for video conferences

Intercom Systems

Separate slave (microcontroller) and master

(Flash) SPI ports, maximum clock rate = 25 MHz

•

5 General Purpose Input/Output (GPIO) pins

General purpose UART port

Security Systems

OSCo

100 MHz MCLK

CODEC[0]

APLL

OSC

Interrupt

ADC

OSCi

Instruction

Memory

Controller

DAC

Bytes

ROM

RAM

Driver

DSP

27K

Bytes

Core

Timing

Generator

CODEC[1:0]

CODEC[1]

Device Clocks

ADC

DAC

Hardware

Accelerator

Data RAM

Master

SPI

24K

Bytes

Filter

Co-processor

Driver

Slave

SPI

PCM

I²S

UART

GPIO

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7

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