Datasheet > ZL38005

ZL38005

更新时间： 2024-11-19 03:08:35

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		解码器编解码器
页数	文件大小	规格书
8页	116K
描述
Enhanced Voice Processor with Dual Wideband Codecs

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数据手册

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ZL38005 数据手册

ZL38005

Enhanced Voice Processor

with Dual Wideband Codecs

Data Sheet

September 2007

Features

Ordering Information

•

100 MHz (200 MIPs) Zarlink voice processor with

hardware accelerator.

ZL38005QCG1 100 Pin LQFP*

Trays, Bake &

•

Dual narrow band (8 KHz) ∆Σ ADCs with input

Drypack

ZL38005GGG2 96 Pin CABGA* Trays, Bake &

Drypack

buffer gain selection

•

Dual narrow band (8 KHz) ∆Σ DACs

Dual function Inter-IC Sound (I²S) port

*Pb Free Matte Tin

-40°C to +85°C

PCM port supports TDM (ST BUS, GCI or McBSP

framing) or SSI modes at bit rates of 128, 256, 512,

1024, 2048, 4096, 8192 or 16384 Kb/sec

Applications

•

Hands-free car kits

•

Separate slave (microcontroller) and master

(Flash) SPI ports, maximum clock rate = 25 MHz

Full duplex speaker-phone for digital telephone

Echo cancellation for video conferences

Intercom Systems

•

11 General Purpose Input/Output (GPIO) pins

General purpose UART port

Bootloadable for future Zarlink software upgrades

External oscillator or crystal/ceramic resonator

1.2 V Core; 3.3 V IO with 5 V-tolerant inputs

IEEE-1149.1 compatible JTAG port

Security Systems

Buffer

OSCo

CODEC[0]

APLL

OSC

Interrupt

ADC

OSCi

PCM_CLKi

Instruction

Memory

Controller

DAC

PCM_LBCi

PCM P0

Clock

ROM

Driver

Buffer

JTAG

DSP

Core

Timing

Generator

RAM

CODEC[1]

ADC

DAC

Master

SPI

Data RAM

Hardware

Driver

Accelerator

Slave

SPI

PCM P0

IRQ

I²S

UART

GPIO

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7 8

中文翻译

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与ZL38005相关器件

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ZL38005GGG2	ZARLINK	获取价格	Enhanced Voice Processor with Dual Wideband Codecs
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ZL38005QCG1	ZARLINK	获取价格	Enhanced Voice Processor with Dual Wideband Codecs
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ZL38010DCE1	ZARLINK	获取价格	Low Power Quad ADPCM Transcoder
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