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ZL30622 PDF预览

ZL30622

更新时间: 2024-11-20 14:55:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
96页 1337K
描述
The ZL30622 is a?fully compliant SEC (G.813) and EEC (G.8262) single channel Network Synchronizer

ZL30622 数据手册

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Register Map: Section 6.2  
ZL30622  
3-Input, 3-Output Any-to-Any Frequency  
Timing Card PLL with Ultra-Low Jitter  
Data Sheet  
January 2018  
Ordering Information  
Features  
ZL30622LDG1  
ZL30622LDF1  
32 Pin QFN  
32 Pin QFN  
Trays  
Tape and Reel  
Low-Bandwidth DPLL  
ITU-T G.813/G.8262 compliance (options 1 & 2)  
Programmable bandwidth, 0.1Hz to 500Hz  
Attenuates jitter up to several UI  
Freerun or holdover on loss of all inputs  
Hitless reference switching  
Matte Tin  
Package size: 5 x 5 mm  
-40 C to +85 C  
In 2xCMOS mode, the P and N pins can be  
different frequencies (e.g. 125MHz and 25MHz)  
High-resolution holdover averaging  
Digitally controlled phase adjustment  
Per-output supply pin with CMOS output  
voltages from 1.5V to 3.3V  
Input Clocks  
Precise output alignment circuitry and per-  
Three inputs, two differential/CMOS, one CMOS  
output phase adjustment  
Any input frequency from 8kHz to 1250MHz  
Per-output enable/disable and glitchless  
(8kHz to 300MHz for CMOS)  
start/stop (stop high or low)  
Per-input activity and frequency monitoring  
Automatic or manual reference switching  
General Features  
Automatic self-configuration at power-up from  
internal EEPROM; up to four configurations  
pin-selectable  
Low-Jitter Fractional-N APLL and 3 Outputs  
Any output frequency from <1Hz to 1035MHz  
Numerically controlled oscillator mode  
Input-to-output alignment with external feedback  
SPI or I2C processor Interface  
High-resolution fractional frequency conversion  
with 0ppm error  
Encapsulated design requires no external  
VCXO or loop filter components  
Easy-to-use evaluation software  
Output jitter as low as 0.25ps RMS (12kHz-  
Applications  
20MHz integration band)  
Telecom timing cards for SONET/SDH, SyncE,  
wireless base stations and other systems  
Outputs are CML or 2xCMOS, can interface to  
LVDS, LVPECL, HSTL, SSTL and HCSL  
IC1P, IC1N  
OC1P, OC1N  
VDDO1  
OC2P, OC2N  
VDDO2  
OC3P, OC3N  
VDDO3  
HSDIV1  
HSDIV1  
HSDIV2  
DIV1  
DIV2  
DIV3  
DPLL  
Hitless Switching,  
Jitter Filtering,  
Holdover  
APLL  
~3.7 to 4.2GHz,  
Fractional-N  
Input Block  
Divider,  
IC2P, IC2N  
IC3P/GPIO3  
Monitor,  
HSDIV2  
HSDIV3  
Selector  
Figure 4  
Figure 5  
Figure 6  
Microprocessor Port  
(SPI or I2C Serial)  
and HW Control and Status Pins  
XA  
xtal  
driver  
TCXO  
×2  
XB  
Figure 1 - Functional Block Diagram  
1
Microsemi Confidential  
Copyright 2018. Microsemi Corporation. All Rights Reserved.  
 

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