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ZL30621 PDF预览

ZL30621

更新时间: 2024-11-24 14:47:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
99页 1413K
描述
The ZL30621 is a?fully compliant SEC (G.813) and EEC (G.8262) single channel Network Synchronizer

ZL30621 数据手册

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Register Map: Section 6.2  
ZL30621  
3-Output Any Frequency Timing Card  
PLL with Ultra-Low Jitter  
Data Sheet  
January 2018  
Features  
Ordering Information  
Low-Bandwidth DPLL  
ZL30621LFG7  
ZL30621LFF7  
64 Pin LGA  
64 Pin LGA  
Trays  
Tape and Reel  
ITU-T G.813/G.8262 compliance (options 1 & 2)  
Ni Au  
Low-jitter operation from any 10MHz TCXO  
Package size: 5 x 10 mm  
Master clock jitter attenuator reduces cost by  
-40 C to +85 C  
removing TCXO/OCXO low-jitter requirement  
Programmable bandwidth, 0.1Hz to 10Hz  
Attenuates input clock jitter up to several UI  
Hitless reference switching  
Outputs are CML or 2xCMOS, can interface to  
LVDS, LVPECL, HSTL, SSTL and HCSL  
In 2xCMOS mode, the P and N pins can be  
different frequencies (e.g. 125MHz and 25MHz)  
High-resolution holdover averaging  
Digitally controlled phase adjustment  
Input Clocks  
Per-output supply pin with CMOS output  
voltages from 1.5V to 3.3V  
Precise output alignment circuitry and per-  
output phase adjustment  
Up to 3 inputs, 2 differential/CMOS, one CMOS  
Per-output enable/disable and glitchless  
Any input frequency from 8kHz to 1250MHz  
start/stop (stop high or low)  
(8kHz to 300MHz for CMOS)  
General Features  
Per-input activity and frequency monitoring  
Automatic or manual reference switching  
Automatic self-configuration at power-up from  
internal EEPROM; up to four configurations  
pin-selectable  
Low-Jitter Fractional-N APLL and 3 Outputs  
Any output frequency from <1Hz to 1035MHz  
Numerically controlled oscillator mode  
Input-to-output alignment with external feedback  
SPI or I2C processor Interface  
High-resolution fractional frequency conversion  
with 0ppm error  
Encapsulated design requires no external  
Easy-to-use evaluation software  
VCXO or loop filter components  
Each output has independent dividers  
Applications  
Telecom timing cards for SONET/SDH, SyncE,  
wireless base stations and other systems  
Output jitter as low as 0.25ps RMS (12kHz-  
20MHz integration band)  
IC1P_A, IC1N_A  
OC1P_A, OC1N_A  
VDDO1_A  
OC2P_A, OC2N_A  
VDDO2_A  
OC3P_A, OC3N_A  
VDDO3_A  
HSDIV1  
HSDIV1  
HSDIV2  
DIV1  
DIV2  
DIV3  
DPLL  
G.8262 Compliance  
Hitless Switching,  
Jitter Filtering,  
Holdover  
APLL  
~3.7 to 4.2GHz,  
Fractional-N  
Input Block  
Divider,  
IC2P_A, IC2N_A  
IC3P_A, IC3N_A  
Monitor,  
HSDIV2  
HSDIV3  
Selector  
Figure 10  
Figure 8  
Figure 9  
MCLK  
multiplier  
& JA  
MCLK Multiplier Processor Port  
(SPI or I2C Serial)  
DPLL Processor Port  
(SPI or I2C Serial)  
and HW Control and Status Pins  
IC3P_B  
and HW Control and Status Pins  
TCXO  
configuration 2 only à crystal  
Figure 1 - Functional Block Diagram  
1
Microsemi Confidential  
Copyright 2018. Microsemi Corporation. All Rights Reserved.  
 

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