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ZL30416GGG2 PDF预览

ZL30416GGG2

更新时间: 2024-11-19 03:05:59
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 时钟
页数 文件大小 规格书
22页 872K
描述
SONET/SDH Clock Multiplier PLL

ZL30416GGG2 技术参数

生命周期:Transferred包装说明:LFBGA,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.81应用程序:SONET;SDH
JESD-30 代码:S-PBGA-B64JESD-609代码:e1
长度:8 mm功能数量:1
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.41 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:INDUSTRIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:8 mm
Base Number Matches:1

ZL30416GGG2 数据手册

 浏览型号ZL30416GGG2的Datasheet PDF文件第2页浏览型号ZL30416GGG2的Datasheet PDF文件第3页浏览型号ZL30416GGG2的Datasheet PDF文件第4页浏览型号ZL30416GGG2的Datasheet PDF文件第5页浏览型号ZL30416GGG2的Datasheet PDF文件第6页浏览型号ZL30416GGG2的Datasheet PDF文件第7页 
ZL30416  
SONET/SDH Clock Multiplier PLL  
Data Sheet  
June 2006  
Features  
Low jitter clock outputs suitable for OC-192, OC-  
Ordering Information  
48, OC-12, OC-3 and OC-1 SONET applications  
as defined in Telcordia GR-253-CORE  
ZL30416GGG  
64 Ball CABGA Trays, Bake & Drypack  
ZL30416GGG2 64 Ball CABGA* Trays, Bake & Drypack  
Low jitter clock outputs suitable for STM-64, STM-  
16, STM-4 and STM-1 applications as defined in  
ITU-T G.813  
*Pb Free Tin/Silver/Copper  
-40°C to +85°C  
Provides one differential LVPECL output clock  
selectable to 19.44, 38.88, 77.76, 155.52 or  
622.08 MHz  
Description  
The ZL30416 is an Analog Phase-Locked Loop (APLL)  
designed to provide jitter attenuation and rate  
conversion for SDH (Synchronous Digital Hierarchy)  
and SONET (Synchronous Optical Network)  
networking equipment. The ZL30416 generates low  
jitter output clocks suitable for Telcordia GR-253-  
CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and  
ITU-T G.813 STM-64, STM-16, STM-4 and STM-1  
applications.  
Provides a single-ended CMOS output clock at  
19.44 MHz  
Accepts a single-ended CMOS reference at  
19.44 MHz or a differential LVDS, LVPECL or  
CML reference at 19.44 or 77.76 MHz  
Provides a LOCK indication  
8 mm x 8 mm CABGA package  
3.3 V supply  
The ZL30416 accepts a CMOS compatible reference  
at 19.44 MHz or a differential LVDS, LVPECL or CML  
reference at 19.44 or 77.76 MHz and generates a  
differential LVPECL output clock selectable to 19.44,  
38.88, 77.76, 155.52 or 622.08 MHz and a single-  
ended CMOS clock at 19.44 MHz. The ZL30416  
provides a lock indication.  
Applications  
SONET/SDH line cards  
LPF  
REF_SEL  
FS3 FS2 FS1  
C19o, C38o, C77o,  
C155o, C622o,  
LVPECL output  
C19i  
Frequency  
& Phase  
Loop  
Filter  
VCO  
Reference  
Selection  
MUX  
OC-CLKoP/N  
C19o  
Frequency  
Dividers  
and  
Detector  
REFinP/N  
19.44 MHz and 77.76 MHz  
Clock  
Drivers  
Reference  
and  
C19i or C77i  
CML, LVDS,  
LVPECL input  
State  
Machine  
Bias Circuit  
REF_FREQ LOCK  
BIAS  
VCC GND VDD  
C19oEN  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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