Datasheet > ZL30416

ZL30416

更新时间： 2024-11-18 21:54:27

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		时钟
页数	文件大小	规格书
22页	342K
描述
SONET/SDH Clock Multiplier PLL

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ZL30416 数据手册

ZL30416

SONET/SDH Clock Multiplier PLL

Data Sheet

November 2004

Features

•

Low jitter clock outputs suitable for OC-192, OC-

48, OC-12, OC-3 and OC-1 SONET applications

as defined in Telcordia GR-253-CORE

Ordering Information

ZL30416GGG

64 Ball CABGA

Low jitter clock outputs suitable for STM-64, STM-

16, STM-4 and STM-1 applications as defined in

ITU-T G.813

-40°C to +85°C

Provides one differential LVPECL output clock

selectable to 19.44, 38.88, 77.76, 155.52 or

622.08 MHz

Description

The ZL30416 is an Analog Phase-Locked Loop (APLL)

designed to provide jitter attenuation and rate

conversion for SDH (Synchronous Digital Hierarchy)

and SONET (Synchronous Optical Network)

networking equipment. The ZL30416 generates low

jitter output clocks suitable for Telcordia GR-253-

CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and

ITU-T G.813 STM-64, STM-16, STM-4 and STM-1

applications.

•

Provides a single-ended CMOS output clock at

19.44 MHz

Accepts a single-ended CMOS reference at

19.44 MHz or a differential LVDS, LVPECL or

CML reference at 19.44 or 77.76 MHz

•

Provides a LOCK indication

8 mm x 8 mm CABGA package

3.3 V supply

The ZL30416 accepts a CMOS compatible reference

at 19.44 MHz or a differential LVDS, LVPECL or CML

reference at 19.44 or 77.76 MHz and generates a

differential LVPECL output clock selectable to 19.44,

38.88, 77.76, 155.52 or 622.08 MHz and a single-

ended CMOS clock at 19.44 MHz. The ZL30416

provides a lock indication.

Applications

•

SONET/SDH line cards

LPF

REF_SEL

FS3 FS2 FS1

C19o, C38o, C77o,

C155o, C622o,

LVPECL output

C19i

Frequency

& Phase

Detector

Loop

Filter

VCO

Reference

Selection

MUX

OC-CLKoP/N

C19o

Frequency

Dividers

and

Clock

Drivers

REFinP/N

19.44 MHz and 77.76 MHz

Reference

and

Bias Circuit

C19i or C77i

CML, LVDS,

LVPECL input

State

Machine

REF_FREQ LOCK

BIAS

VCC GND VDD

C19oEN

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...22

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