Datasheet > ZL30154

ZL30154

更新时间： 2023-12-06 20:03:39

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
181页	890K
描述
The ZL30154 Synchronous Ethernet Network Synchronizer, part of Microchip's ClockCenter platform is

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ZL30154 数据手册

ZL30154

Synchronous Ethernet Network

Synchronization DPLL

Data Sheet

March 2015

Features

Ordering Information

•

Supports requirements of ITU-T G.8262 for

ZL30154GGG2 100 Pin LBGA*

Trays

Synchronous Ethernet Equipment Slave Clocks

(EEC option 1 and 2)

*Pb Free Tin/Silver/Copper

-40^oC to +85^oC

•

Supports requirements of Telcordia GR-1244

Stratum 3 and GR-253, ITU-T G.813, and G.781

SETS

•

Digital PLLs filter jitter from 0.1 mHz, 1 mHz,

10 mHz, 0.1 Hz, 1.7 Hz, 3.6 Hz, 7 Hz, 14 Hz,

28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz

•

Supports ITU-T G.823, G.824 and G.8261 for

2048 kbit/s and 1544 kbit/s interfaces

•

Automatic hitless reference switching and digital

holdover on reference fail

Programmable synthesizers generate any clock-

rate from 1 Hz to 750 MHz

Four reference inputs configurable as single

ended or differential

Two precision synthesizers generate clocks with

jitter below 0.7 ps RMS for 10 G PHYs

•

Eight LVPECL outputs and four LVCMOS outputs

Two general purpose synthesizers generate a wide

range of digital bus clocks

Eight outputs configurable as LVCMOS or

LVDS/LVPECL/HCSL

Programmable digital PLLs synchronize to any

clock rate from 1 Hz to 750 MHz

•

Operates from a single crystal resonator or clock

oscillator

Flexible two-stage architecture translates between

arbitrary data rates, line coding rates and FEC

rates

Customer defined default device configuration,

including input/output frequencies, is available via

OTP(One Time Programmable) memory

Figure 1 - Functional Block Diagram

Microsemi Corporation

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