Datasheet > ZL30151

ZL30151

更新时间： 2023-12-06 20:02:07

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
102页	2265K
描述
The ZL30151 is a high performance line card device in a tiny 5x5mm package.? The device accepts up

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ZL30151 数据手册

ZL30151

3-Input, 3-Output Any-to-Any Line Card

PLL with Ultra-Low Jitter

Data Sheet

January 2018

Ordering Information

Features

ZL30151LDG1

ZL30151LDF1

32 Pin QFN

Trays

Tape and Reel

• Input Clocks

• Three inputs, two differential/CMOS, one CMOS

Matte Tin

• Any input frequency from 1kHz to 650MHz

Package size: 5 x 5 mm

(1kHz to 300MHz for CMOS)



-40 C to +85 C

• Inputs continually monitored for activity and

frequency accuracy

• In 2xCMOS mode, the P and N pins can be

• Automatic or manual reference switching

different frequencies (e.g. 125MHz and 25MHz)

• Per-output supply pin with CMOS output

• Low-Bandwidth DPLL

voltages from 1.5V to 3.3V

• Programmable bandwidth, 1Hz to 500Hz

• Attenuates jitter up to several UI

• Freerun or holdover on loss of all inputs

• Hitless reference switching

• Precise output alignment circuitry and per-

output phase adjustment

• Per-output enable/disable and glitchless

start/stop (stop high or low)

• General Features

• High-resolution holdover averaging

• Digitally controlled phase adjustment

• Automatic self-configuration at power-up from

internal EEPROM; up to four configurations

pin-selectable

• Low-Jitter Fractional-N APLL and 3 Outputs

• Any output frequency from <1Hz to 650MHz

• Numerically controlled oscillator mode

• Zero-delay mode with external feedback

• SPI or I²C processor Interface

• High-resolution fractional frequency conversion

with 0ppm error

• Easy-to-use evaluation software

• Easy-to-configure, encapsulated design

requires no external VCXO or loop filter

components

Applications

•

Telecom line cards for SONET/SDH, PDH,

Synchronous Etherenet, Fibre Channel

• Each output has independent dividers

•

Broadcast video equipment

• Output jitter is typically 0.16 to 0.28ps RMS

(12kHz-20MHz integration band)

Frequency conversion and jitter attenuation in a

wide variety of equipment types

• Outputs are CML or 2xCMOS, can interface to

LVDS, LVPECL, HSTL, SSTL and HCSL

IC1P, IC1N

OC1P, OC1N

VDDO1

OC2P, OC2N

VDDO2

OC3P, OC3N

VDDO3

HSDIV1

HSDIV2

DIV1

DIV2

DIV3

DPLL

Hitless Switching,

Jitter Filtering,

Holdover

APLL

~3.7 to 4.2GHz,

Fractional-N

Input Block

Divider,

IC2P, IC2N

IC3P/GPIO3

Monitor,

HSDIV2

HSDIV3

Selector

Figure 9

Figure 10

Figure 11

Microprocessor Port

(SPI or I2C Serial)

and HW Control and Status Pins

xtal

driver

×2

Figure 1 - Functional Block Diagram

Microsemi Confidential

12 3 4 5 6 7...102

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