Datasheet > ZL30146GGG

ZL30146GGG

更新时间： 2024-01-19 19:34:17

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
4页	76K
描述
Telecom IC,

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技术参数
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ZL30146GGG 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.68
Base Number Matches：	1

ZL30146GGG 数据手册

ZL30146

SyncE SONET/SDH Line Card PLL

Short Form Data Sheet

July 2009

Features

Ordering Information

•

Synchronizes to standard telecom or Ethernet

backplane clocks and provides jitter filtered output

clocks for SONET/SDH, PDH and Ethernet network

interface cards

ZL30146GGG

ZL30146GGG2 64 Pin CABGA*

64 Pin CABGA

Trays

*Pb Free Tin/Silver/Copper

-40^oC to +85^oC

•

Supports the requirements of ITU-T G.8262 for

synchronous Ethernet Equipment slave Clocks

Meets the SONET/SDH jitter generation

requirements up to OC-192/STM-64

•

Programmable output synthesizer to generate

telecom clock frequencies from any multiple of

8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3)

Two independent DPLLs provides timing for the

transmit path (backplane to line rate) and the

receive path (recovered line rate to backplane)

•

Generates several styles of output frame pulse

with selectable pulse width, polarity, and frequency

•

Synchronizes to telecom reference clocks (2 kHz,

N*8 kHz up to 77.76 MHz, 155.52 MHz) or to

Ethernet reference clocks (25 MHz, 50 MHz,

62.5 MHz, 125 MHz)

Configurable input to output delay and output to

output phase alignment

Configurable through a serial interface (SPI or I²C)

•

Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,

3.5 Hz, 1.7 Hz, or 0.1 Hz

DPLLs can be configured to provide synchronous

or asynchronous clock outputs

Supports automatic hitless reference switching and

short term holdover during loss of reference inputs

Applications

Generates standard SONET/SDH clock rates (e.g.,

19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,

622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,

50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for

synchronizing Ethernet PHYs

•

ITU-T G.8262 Line Cards which support 1 GbE

and 10 GbE interfaces

•

SONET/SDH line cards up to OC-192/STM-64

osci

osco

ref0

ref1

ref2

ref3

ref4

p_clk

p_fp

Programmable

Synthesizer

N*8kHz

Rx DPLL

ref_m

Input

Ports

ref_n/sync_n

sync0

diff

Ethernet/

SONET

APLL

Tx DPLL

apll_clk

Ref/Sync

Monitors

mode hold lock

I2C/SPI

JTAG

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4

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