Datasheet > ZL30145

ZL30145

更新时间： 2024-10-02 14:54:55

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
58页	680K
描述
The ZL30145 is a highly integrated device that provides timing for line cards. The DPLL automatica

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ZL30145 数据手册

ZL30145

SyncE (10 GbE) SONET/SDH Rate

Conversion and Jitter Attenuator PLL

Data Sheet

March 2013

Features

Ordering Information

•

Can be used in systems to support the

ZL30145GGG

ZL30145GGG2 64 Pin CABGA* Trays

64 Pin CABGA Trays

requirements of ITU-T G.8262 for synchronous

Ethernet Equipment slave Clocks (EEC option 1

and 2)

*Pb Free Tin/Silver/Copper

-40 C to +85 C

•

Meets jitter generation requirements of Telcordia

GR-253-CORE for OC-192, OC-48, OC-12 and

OC-3 rates

•

Configurable through a serial interface (SPI or I C)

DPLL can be configured to provide synchronous or

asynchronous clock outputs

•

Meets jitter generation requirements of ITU-T G.813

for STM-64, STM-16, STM-4 and STM-1 rates

•

Supports IEEE 1149.1 JTAG Boundary Scan

Synchronizes to standard telecom or Ethernet clock

and provides jitter filtered output clock for

SONET/SDH and Synchronous Ethernet line cards

Applications

•

Synchronizes to telecom reference clocks (2 kHz,

N*8 kHz up to 77.76 MHz, 155.52 MHz) or to

Ethernet reference clocks (25 MHz, 50 MHz,

62.5 MHz, 125 MHz)

•

ITU-T G.8262 Line Cards which support 1 GbE

and 10 GbE interfaces

•

SONET line cards up to OC-192

SDH line cards up to STM-64

Generates standard SONET/SDH clock rates (e.g.,

19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,

622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,

50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for

synchronizing Ethernet PHYs

•

Selectable loop bandwidth of 14 Hz, 28 Hz, or

890 Hz

osci

osco

SONET/SDH/

diff

Ethernet

DPLL

ref

apll_clk

APLL

I²C/SPI

JTAG

hold

lock

Figure 1 - Simplified Functional Block Diagram

12 3 4 5 6 7...58

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