ZL30143
SyncE SONET/SDH
G.8262/Stratum3SystemSynchronizer/SETS
Data Sheet
March 2013
Features
Ordering Information
•
Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
ZL30143GGG
100 Pin CABGA Trays
ZL30143GGG2 100 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
•
Supports the requirements of Telcordia GR-1244
Stratum 3 and GR-253, ITU-T G.813, and G.781
SETS
o
o
-40 C to +85 C
•
•
•
Supports ITU-T G.823, G.824 and G.8261 for 2048
kbit/s and 1544 kbit/s interfaces
•
•
Internal state machine automatically controls
mode of operation (free-run, locked, holdover)
Meets the SONET/SDH jitter generation
requirements up to OC-48/STM-16
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
•
•
Provides automatic reference switching and
holdover during loss of reference input
Supports master/slave configuration and dynamic
input to output delay compensation for
•
•
Supports composite clock inputs (64 kHz, 64 kHz +
8 kHz, 64kHz + 8 kHz + 400 Hz)
TM
AdvancedTCA
Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Gigabit Ethernet PHYs
•
Configurable input to output delay and output to
output phase alignment
Applications
•
•
•
ITU-T G.8262 System Timing Cards which support
1 GbE and 10 GbE interfaces
•
Programmable output synthesizers (P0, P1)
generate telecom clock frequencies from any
multiple of 8 kHz up to 100 MHz
Telcordia GR-253 Carrier Grade SONET/SDH
Stratum 3 System Timing Cards
•
•
Generates several styles of telecom frame pulses
with selectable pulse width, polarity and frequency
System Timing Cards which supports ITU-T G.781
SETS (SDH Equipment Timing Source)
Provides two DPLLs which are independently
configurable through a serial interface
Figure 1 - Functional Block Diagram
1
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