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ZL30138 PDF预览

ZL30138

更新时间: 2023-12-06 20:06:16
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
163页 2513K
描述
The ZL30138 SONET/SDH/Ethernet Stratum 2/3E/3 System Synchronizer and SETS device is a highly inte

ZL30138 数据手册

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ZL30138  
OC-192/STM-64 SONET/SDH/10GbE  
Stratum 2/3/3E System Synchronizer/SETS  
Data Sheet  
March 2013  
Features  
Ordering Information  
Supports the requirements of ITU-T G.8262 for  
synchronous Ethernet Equipment slave Clocks  
(EEC option 1 and 2)  
ZL30138GGG 100 Pin CABGA Trays  
ZL30138GGG2 100 Pin CABGA* Trays  
*Pb Free Tin/Silver/Copper  
Supports the requirements of Telcordia GR-1244  
Stratum 2/3/3E and GR-253, ITU-T G.812, G.813,  
and G.781 SETS  
o
o
-40 C to +85 C  
Supports ITU-T G.823, G.824 and G.8261 for  
2048kbits/s and 1544kbits.s interfaces  
Generates several styles of telecom frame pulses  
with selectable pulse width, polarity and  
frequency  
Meets the SONET/SDH jitter generation  
requirements up to OC-192/STM-64  
Provides two DPLLs which are independently  
configurable through a serial interface  
Synchronizes to telecom reference clocks (2 kHz,  
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to  
Ethernet reference clocks (25 MHz, 50 MHz,  
62.5 MHz, 125 MHz)  
Internal state machine automatically controls  
mode of operation (free-run, locked, holdover)  
Flexible input reference monitoring automatically  
disqualifies references based on frequency and  
phase irregularities  
Supports composite clock inputs (64 kHz, 64 kHz  
+ 8 kHz, 64kHz + 8 kHz + 400 Hz)  
Generates standard SONET/SDH clock rates  
(e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz,  
155.52 MHz, 622.08 MHz) or Ethernet clock rates  
(e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz,  
312.5 MHz) for synchronizing Gigabit Ethernet  
PHYs  
Provides automatic reference switching and  
holdover during loss of reference input  
Supports master/slave configuration and dynamic  
input to output delay compensation for  
TM  
AdvancedTCA  
Configurable input to output delay and output to  
output phase alignment  
Programmable output synthesizers (P0, P1)  
generate telecom clock frequencies from any  
multiple of 8 kHz up to 100 MHz  
Figure 1 - Functional Block Diagram  
1
Copyright 2013, Microsemi Corporation. All Rights Reserved.  

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